公开(公告)号：US20250013376A1

公开(公告)日：2025-01-09

申请号：US18890110

申请日：2024-09-19

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including obtaining, from a host system, a power safety configuration for a partition, wherein the power safety configuration for the partition configures the memory device to implement power safe writing for the partition by operating in a first write mode utilizing single level cell (SLC) caching, or to implement non-power safe writing for the partition by operating in a second write mode without utilizing SLC caching, and configuring the memory device to operate in the first write mode or the second write mode based on the power safety configuration.

公开(公告)号：US20240295993A1

公开(公告)日：2024-09-05

申请号：US18647677

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Xinghui Duan ,  Massimo Zucchinali

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7202

Abstract: A computing system having a storage system that includes a storage device and a host device, where the host device is configured to issue memory access commands to the storage device. The computing system further includes a prediction system comprising processing circuitry that is configured to perform operations that cause the prediction system to identify one or more components of the storage system that limit random read performance of the storage system. The operations further cause the prediction system to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system. The operations additionally cause the prediction system to execute the model in a simulation of the storage system to generate a random read performance parameter for the storage system.

公开(公告)号：US20240281369A1

公开(公告)日：2024-08-22

申请号：US18581270

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0261 ,  G06F13/1668

Abstract: Methods, systems, and devices for a partitioned cache for random read operations are described. Implementations may determine a target compression factor that is used during read operations. Larger compression factors may be associated with more frequent penalties, but may allow for a larger high-performance benchmark on a large address range. As described herein, a compression factor may indicate certain mappings that are stored to a volatile memory. The compression factor may be chosen at product design time or may be chosen dynamically at run time based on statistics such as extended cache hit or miss rate. If a read command associated with a logical block address not stored by the volatile memory is received, the memory system may “guess” the physical address by assuming that data was written to the memory system sequentially. If the data is correct, the data may be read out to the host system.

公开(公告)号：US11988563B2

公开(公告)日：2024-05-21

申请号：US17153107

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C16/04 ,  G01K1/02 ,  G01K1/022 ,  G05B19/042 ,  G06F16/2455

CPC classification number: G01K1/022 ,  G01K1/028 ,  G05B19/0428 ,  G06F16/24558

Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

公开(公告)号：US20240053895A1

公开(公告)日：2024-02-15

申请号：US17887258

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Giuseppe Cariello ,  David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0629

Abstract: Methods, systems, and devices for improving write quality in memory systems are described. The memory system may receive, from a host system, a command to perform an operation. The memory system may determine an availability parameter that indicates processing resources of the memory system that are available to perform the operation based on receiving the command. In some cases, the memory system may transmit, to the host system, a message comprising the availability parameter, and the host system may delay transmission of one or more pending commands based on receiving the message comprising the availability parameter.

公开(公告)号：US20240053894A1

公开(公告)日：2024-02-15

申请号：US17884429

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Giuseppe Cariello ,  Fulvio Rori

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679 ,  G06F3/0659

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

公开(公告)号：US11868632B2

公开(公告)日：2024-01-09

申请号：US17736605

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0625 ,  G06F3/0679

Abstract: Methods, systems, and devices for power control for boot-up of memory systems are described. A memory system may be configured to boot-up using two different power modes: a lower-power mode, and a higher-power mode. The memory system may perform a series of evaluations to determine whether the memory system is to switch to the lower-power mode during boot-up operations, or stay in the higher-power mode. For example, the memory system may check one or more of: a history of previous boot-up failures, a voltage of an associated power management integrated circuit, a history of asynchronous power loss at the device, a power-mode configuration of the host device, or a history of host-initiated power-down commands. In some examples, by switching to the lower-power mode, the memory system may avoid repeatedly failing multiple boot-up cycles and may instead successfully boot-up the memory system.

公开(公告)号：US20230214294A1

公开(公告)日：2023-07-06

申请号：US17647700

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F12/02

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1417 ,  G06F11/142 ,  G06F12/0238

Abstract: Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.

公开(公告)号：US20230214137A1

公开(公告)日：2023-07-06

申请号：US17736605

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0625 ,  G06F3/0679

Abstract: Methods, systems, and devices for power control for boot-up of memory systems are described. A memory system may be configured to boot-up using two different power modes: a lower-power mode, and a higher-power mode. The memory system may perform a series of evaluations to determine whether the memory system is to switch to the lower-power mode during boot-up operations, or stay in the higher-power mode. For example, the memory system may check one or more of: a history of previous boot-up failures, a voltage of an associated power management integrated circuit, a history of asynchronous power loss at the device, a power-mode configuration of the host device, or a history of host-initiated power-down commands. In some examples, by switching to the lower-power mode, the memory system may avoid repeatedly failing multiple boot-up cycles and may instead successfully boot-up the memory system.

公开(公告)号：US11693769B2

公开(公告)日：2023-07-04

申请号：US17527776

申请日：2021-11-16

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/16 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G06F12/0253 ,  G11C11/1659 ,  G11C16/10 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7211 ,  G11C16/0483 ,  G11C16/3495 ,  G11C2211/5641

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.