公开(公告)号：US20200052070A1

公开(公告)日：2020-02-13

申请号：US16514827

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423

Abstract: Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region gatedly coupled with a second source/drain region. A digit line is coupled with the first source/drain region. A charge-storage device is coupled with the second source/drain region through an interconnect. The interconnect includes a length of a semiconductor material. A protective transistor gates a portion of the length of the semiconductor material.

公开(公告)号：US20200043541A1

公开(公告)日：2020-02-06

申请号：US16544587

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US10535399B2

公开(公告)日：2020-01-14

申请号：US16137971

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/24 ,  G11C11/4097 ,  G11C7/02 ,  G11C11/408 ,  G11C11/4094 ,  H01L27/108 ,  F21S41/25 ,  F21S41/663 ,  F21S41/265 ,  F21S41/37 ,  F21S41/125 ,  F21S41/143 ,  F21S41/255 ,  F21S41/43 ,  F21S41/64 ,  G02B27/18 ,  G11C11/4091

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20200005853A1

公开(公告)日：2020-01-02

申请号：US16569588

申请日：2019-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/22 ,  H01L27/11507 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US20190325940A1

公开(公告)日：2019-10-24

申请号：US16503356

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/408 ,  H01L27/108 ,  G11C11/4097 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L29/78 ,  H01L49/02 ,  H01L27/02

Abstract: Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

公开(公告)号：US10431283B2

公开(公告)日：2019-10-01

申请号：US16131969

申请日：2018-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C7/02 ,  G11C11/22 ,  G11C11/4091 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11507 ,  G11C11/56

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US10360966B2

公开(公告)日：2019-07-23

申请号：US15854529

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C7/14 ,  G11C11/4099 ,  G11C5/06 ,  G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US20190163349A1

公开(公告)日：2019-05-30

申请号：US15966483

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Patrick Mullarkey

IPC: G06F3/0484 ,  G06F17/30 ,  G06F3/00

Abstract: A system, apparatuses such as a non-transitory readable medium, and a method for generating a geospatial interactive composite web-based image map are disclosed. The system may be configured to receive, from a user device, a request for creating a geospatial interactive composite web-based image map for a selected region of map data displayed by the user device, select images responsive to the request corresponding to defined sub-regions within the selected region of the map data displayed by the user device, construct a collage for the geospatial composite web-based image map responsive to selecting the images, and transmit the collage to the user device for display thereon as an overlay to the map data.

公开(公告)号：US20190049087A1

公开(公告)日：2019-02-14

申请号：US16137971

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: F21S41/25 ,  F21S41/265 ,  F21S41/663 ,  F21S41/125 ,  F21S41/143 ,  F21S41/255 ,  G02B27/18 ,  F21S41/37 ,  F21S41/43 ,  F21S41/64

CPC classification number: G11C11/4097 ,  F21S41/125 ,  F21S41/143 ,  F21S41/25 ,  F21S41/255 ,  F21S41/265 ,  F21S41/37 ,  F21S41/43 ,  F21S41/645 ,  F21S41/663 ,  G02B27/18 ,  G11C7/02 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  H01L27/108

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20180122452A1

公开(公告)日：2018-05-03

申请号：US15854529

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/22 ,  G11C7/14 ,  G11C11/4099

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/4099 ,  G11C2211/5634

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.