公开(公告)号：US11037981B2

公开(公告)日：2021-06-15

申请号：US16560623

申请日：2019-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US20200075476A1

公开(公告)日：2020-03-05

申请号：US16676175

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Ting-Wei Chiang ,  Chung-Te Lin ,  Hui-Zhong Zhuang ,  Li-Chun Tien ,  Sheng-Hsiung Wang

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.

公开(公告)号：US09991158B2

公开(公告)日：2018-06-05

申请号：US14484670

申请日：2014-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien ,  Tsung-Chieh Tsai

IPC: H01L21/28 ,  H01L21/768 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/265

CPC classification number: H01L21/76877 ,  H01L21/2658 ,  H01L21/28008 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment.

公开(公告)号：US20160358902A1

公开(公告)日：2016-12-08

申请号：US15243787

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract translation: 集成电路包括第一层上的第一层。 第一层包括一组第一行。 第一行各有一个长度和宽度。 第一行的长度大于宽度。 集成电路还包括与第一电平不同的第二电平的第二层。 第二层包括一组第二线。 第二行各有一个长度和一个宽度。 第二行的长度大于宽度。 集成电路还包括被配置为将该组第一线的至少一条第一线与该组第二线的至少一条第二线连接的耦合。 联轴器具有长度和宽度。 该组第二线具有在第一方向上的该组第二线的线之间测量的间距。 第一耦合的长度大于或等于音高。

公开(公告)号：US09431381B2

公开(公告)日：2016-08-30

申请号：US14500528

申请日：2014-09-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/092

Abstract: A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if a first CUT layout pattern and a second CUT layout pattern are in compliance with a predetermined spatial resolution requirement. If the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, a merged CUT layout pattern is generated based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern, and a remedial connecting layout pattern is added to a conductive layer layout. The stitching layout pattern corresponds to a carved-out portion of a third gate electrode structure. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the corresponding carved-out portion.

Abstract translation: 公开了一种处理可用于制造集成电路（IC）的栅电极切割（CUT）布局的方法。 该方法包括确定第一CUT布局图案和第二CUT布局图案是否符合预定的空间分辨率要求。 如果第一CUT布局图案和第二CUT布局图案不符合预定的空间分辨率要求，则基于第一CUT布局图案，第二CUT布局图案和拼接布局图案来生成合并的CUT布局图案， 并且补丁连接布局图案被添加到导电层布局。 缝合布局图案对应于第三栅电极结构的雕刻部分。 补救连接布局图案对应于制造电连接第三栅电极结构的两个由相应的雕刻部分分隔的部分的导电特征。

公开(公告)号：US09299734B2

公开(公告)日：2016-03-29

申请号：US14018178

申请日：2013-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC: H01L21/66 ,  H01L27/146 ,  H01L29/78 ,  H01L21/324 ,  H01L21/8238

CPC classification number: H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

Abstract: A method of preparing an active pixel cell on a substrate includes exerting a first stress on the substrate by forming a shallow trench isolation (STI) structure in the substrate. The method further includes testing the stressed substrate using Raman spectroscopy at a plurality of locations on the stress substrate. The method further includes depositing a stress layer having a second stress on the substrate. The stress layer covers devices of the active pixel cell that are on the substrate and the devices include a photodiode next to the STI and a transistor, and the deposition of the stress layer results in the second stress being exerted on the substrate, the second stress countering the first stress.

Abstract translation: 在衬底上制备有源像素单元的方法包括通过在衬底中形成浅沟槽隔离（STI）结构，在衬底上施加第一应力。 该方法还包括在应力衬底上的多个位置使用拉曼光谱测试应力衬底。 该方法还包括在衬底上沉积具有第二应力的应力层。 应力层覆盖在衬底上的有源像素单元的器件，并且器件包括位于STI旁边的光电二极管和晶体管，并且应力层的沉积导致施加在衬底上的第二应力，第二应力 应对第一次压力。

公开(公告)号：US09214356B2

公开(公告)日：2015-12-15

申请号：US14753829

申请日：2015-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun Liu ,  Chung-Te Lin ,  Ming-Feng Shieh ,  Shih-Ming Chang ,  Tsai-Sheng Gau

IPC: H01L21/302 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

Abstract translation: 本公开提供了一种用于在半导体器件中形成图案的方法。 根据一些实施例，该方法包括在衬底上提供衬底和图案化目标层; 在所述图案化目标层上形成一个或多个心轴图案; 通过去除第一心轴图案并去除覆盖第一心轴图案的抗蚀剂层的一部分，在抗蚀剂层中形成开口; 形成与第二心轴图案的侧壁相邻的间隔物; 移除所述第二心轴图案以暴露所述间隔件; 在间隔件上形成贴片图案并与开口对准; 使用贴片图案和间隔件作为掩模元件蚀刻图案化目标层以形成最终图案; 并且去除贴片图案和间隔物以暴露最终图案。

公开(公告)号：US20150303067A1

公开(公告)日：2015-10-22

申请号：US14753829

申请日：2015-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun Liu ,  Chung-Te Lin ,  Ming-Feng Shieh ,  Shih-Ming Chang

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

Abstract translation: 本公开提供了一种用于在半导体器件中形成图案的方法。 根据一些实施例，该方法包括在衬底上提供衬底和图案化目标层; 在所述图案化目标层上形成一个或多个心轴图案; 通过去除第一心轴图案并去除覆盖第一心轴图案的抗蚀剂层的一部分，在抗蚀剂层中形成开口; 形成与第二心轴图案的侧壁相邻的间隔物; 移除所述第二心轴图案以暴露所述间隔件; 在间隔件上形成贴片图案并与开口对准; 使用贴片图案和间隔件作为掩模元件蚀刻图案化目标层以形成最终图案; 并且去除贴片图案和间隔物以暴露最终图案。

公开(公告)号：US09070630B2

公开(公告)日：2015-06-30

申请号：US14090848

申请日：2013-11-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun Liu ,  Chung-Te Lin ,  Ming-Feng Shieh ,  Tsai-Sheng Gau ,  Shih-Ming Chang

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

公开(公告)号：US20250159896A1

公开(公告)日：2025-05-15

申请号：US19023364

申请日：2025-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer, Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L23/528 ,  H10B41/23 ,  H10B51/30 ,  H10D30/69 ,  H10D64/01 ,  H10D64/68

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.