公开(公告)号：US20220013453A1

公开(公告)日：2022-01-13

申请号：US16926447

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768

Abstract: A method includes providing a fin, an isolation structure, and first and second source/drain (S/D) features over the fin; forming an etch mask covering a first portion and exposing a second portion of the fin; removing the second portion of the fin, resulting in a first trench; filling the first trench with a first dielectric feature; removing the etch mask; and applying etching process(es) to remove the first portion of the fin and to partially recess the first S/D feature. The etching process(es) includes an isotropic etching tuned selective to materials of the first S/D feature and not materials of the isolation structure and the first dielectric feature, resulting in a second trench under the first S/D feature and having a gap between a bottom surface of the first S/D feature and a top surface of the isolation structure. The method further includes forming a via in the second trench.

公开(公告)号：US11222892B2

公开(公告)日：2022-01-11

申请号：US16901963

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US20210408249A1

公开(公告)日：2021-12-30

申请号：US17093345

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/768 ,  H01L21/3065

Abstract: A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

公开(公告)号：US20210376076A1

公开(公告)日：2021-12-02

申请号：US17127095

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/092 ,  H01L23/538 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

公开(公告)号：US20210134797A1

公开(公告)日：2021-05-06

申请号：US16929592

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Huan-Chieh Su ,  Kuo-Cheng Chiang

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8234

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

公开(公告)号：US20200043794A1

公开(公告)日：2020-02-06

申请号：US16231613

申请日：2018-12-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Chung-Wei Hsu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L21/768 ,  H01L21/308

Abstract: FinFET device and method of forming the same are provided. The method of forming the FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.

公开(公告)号：US10002796B1

公开(公告)日：2018-06-19

申请号：US15476068

申请日：2017-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Jui-Chien Huang ,  Chun-Hsiung Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311

Abstract: A method of forming a semiconductor device includes forming first and second fin structures on a substrate and a patterned polysilicon structure on first portions of the first and second fin structures. The method further includes depositing an insulating layer on second portions of the first and second fin structures and on the patterned polysilicon structure, which may be followed by selectively removing the insulating layer from the second portions and patterning a first hard mask layer on the second portion of the second fin structure. The method also includes growing a first epitaxial region on the second portion of the first fin structure, removing the patterned first hard mask layer from the second portion of the second fin structure, patterning a second hard mask layer on the first epitaxial region, and growing a second epitaxial region on the second portion of the second fin structure.