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131.发明授权System and method for balancing delay of signal communication paths through well voltage adjustment 有权通过井电压调整来平衡信号通信路径的延迟的系统和方法公开(公告)号：US08051340B2
公开(公告)日：2011-11-01
申请号：US12136359
申请日：2008-06-10
IPC分类号： G01R31/28
CPC分类号： H03K5/133 , H03K2005/00032
摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.
摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。
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公开(公告)号：US07966589B2
公开(公告)日：2011-06-21
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： G06F17/50
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译： 本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号 ，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。
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133.发明授权Digital reliability monitor having autonomic repair and notification capability 有权数字可靠性监控器具有自主修复和通知功能公开(公告)号：US07966537B2
公开(公告)日：2011-06-21
申请号：US12479914
申请日：2009-06-08
IPC分类号： G01R31/28
CPC分类号： G06F1/04
摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.
摘要翻译： 一种用于防止集成电路故障的电路。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。
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134.发明授权Determining relative amount of usage of data retaining device based on potential of charge storing device 有权基于电荷存储装置的潜力确定数据保存装置的相对使用量公开(公告)号：US07913193B2
公开(公告)日：2011-03-22
申请号：US11924935
申请日：2007-10-26
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F17/50
CPC分类号： G06F12/121 , G06F2212/1056 , G11C7/1006
摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.
摘要翻译： 公开了集成电路和设计结构。 集成电路可以包括：数据保持装置; 电荷存储装置，其耦合到数据保持装置，使得数据保持装置的使用触发电荷源对电荷存储装置的充电; 以及用于测量电荷存储装置的电位的装置，所述测量装置通信地耦合到基于所测量的电位确定数据保持装置的相对使用量的计算平均值。
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135.发明授权公开(公告)号：US07873961B2
公开(公告)日：2011-01-18
申请号：US11161330
申请日：2005-07-29
CPC分类号： G06F9/462 , G06F9/4843
摘要： A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.
摘要翻译： 一种用于在单个集成电路上支持同时操作操作系统的方法和系统。 该系统包括管理指令的执行的监控操作系统（SOS），每个指令可在一个操作系统下执行; 寄存器分组成多组寄存器，每组寄存器保持一个操作系统的标识; 以及能够分派指令和附加到指令的标签的调度器，识别操作系统之一的标签和在所识别的操作系统下执行的指令以访问寄存器之一。 当执行指令时，使用一个或多个寄存器，并且被包括在多组寄存器的单组中。 单一集合维护由标签识别的操作系统的标识，并且一个或多个寄存器中的每一个包括与标签相匹配的标识符。
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136.发明授权Determining relative amount of usage of data retaining device based on potential of charge storing device 有权基于电荷存储装置的潜力确定数据保存装置的相对使用量公开(公告)号：US07869298B2
公开(公告)日：2011-01-11
申请号：US12045744
申请日：2008-03-11
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C7/00
CPC分类号： G06F12/121 , G06F12/122
摘要： A system for determining a relative amount of usage of a data retaining device are disclosed. A charge storing device is coupled to a data retaining device in a manner that a use of the data retaining device triggers a charging of the charge storing device. In a period that the data retaining device idles, charges in the charge storing device decay due to natural means. As such, a potential of the charge storing device may be used to indicate an amount of usage of the data retaining device. A comparison of the potentials of two charge storing devices coupled one-to-one to two data retaining devices may be used as a basis to determine a relative amount of usage of each of the two data retaining devices comparing to the other.
摘要翻译： 公开了一种用于确定数据保持装置的相对使用量的系统。 电荷存储装置以数据保持装置的使用触发电荷存储装置的充电的方式耦合到数据保持装置。 在数据保持装置闲置的期间，由于自然的手段，电荷存储装置中的电荷衰减。 因此，可以使用电荷存储装置的电位来指示数据保持装置的使用量。 可以使用将一对一耦合到两个数据保持装置的两个电荷存储装置的电位的比较作为确定两个数据保持装置中的每一个相对于另一个的相对使用量的基础。
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137.发明授权Digital reliability monitor having autonomic repair and notification capability 有权数字可靠性监控器具有自主修复和通知功能公开(公告)号：US07823002B2
公开(公告)日：2010-10-26
申请号：US11772418
申请日：2007-07-02
CPC分类号： G06F1/04
摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.
摘要翻译： 一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。
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138.发明授权Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path 失效用于可配置混合逻辑信号分配路径的灵活多模逻辑元件的设计结构公开(公告)号：US07770139B2
公开(公告)日：2010-08-03
申请号：US11931626
申请日：2007-10-31
申请人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.
摘要翻译： 公开了一种被配置为以多种操作模式之一操作的多模电路的设计结构。 特别地，示例性多模电路可以被配置为以全摆动模式，限制摆动模式，全摆幅至限定摆动转换器模式和限定摆动至全摆幅转换器模式之一进行操作。 多模电路的工作模式可以动态地选择。 一个或多个多模电路可以是用于控制集成电路的信号分配路径或树的性能的可配置分配路径的一部分。
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139.发明授权Method, apparatus and computer program product for dynamically selecting compiled instructions 有权用于动态选择编译指令的方法，装置和计算机程序产品公开(公告)号：US07761690B2
公开(公告)日：2010-07-20
申请号：US11828705
申请日：2007-07-26
申请人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
发明人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
IPC分类号： G06F9/48
CPC分类号： G06F9/3836 , G06F9/3897 , G06F15/7867
摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.
摘要翻译： 一种方法，装置和计算机程序产品动态地选择编译指令进行执行。 接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。 基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。 基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。
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公开(公告)号：US07743270B2
公开(公告)日：2010-06-22
申请号：US11530544
申请日：2006-09-11
CPC分类号： G06F1/04 , G06F1/10 , G06F17/5031 , G06F17/505 , G06F2217/62
摘要： A method, system and computer program product reducing clock noise generated by clock signals in an integrated circuit (IC) are disclosed. Conventional IC design attempts to ensure coincident clock active edge arrival times for all clocked elements. The coincident active clock edges generate coincident noise currents, which elevates the total noise current. The current invention assigns clock arrival times for clocked elements of an IC based on a desired clock arrival time distribution such that active clock edges are not coincident. As a consequence, the total noise would be spread over a large portion of the clock cycle, thus reducing the noise magnitude substantially.
摘要翻译： 公开了减少由集成电路（IC）中的时钟信号产生的时钟噪声的方法，系统和计算机程序产品。 传统IC设计尝试确保所有时钟元件的重合时钟主动边沿到达时间。 重合的有效时钟边沿产生一致的噪声电流，这提高了总的噪声电流。 本发明基于期望的时钟到达时间分布来为IC的时钟元件分配时钟到达时间，使得活动时钟边缘不一致。 因此，总噪声将在时钟周期的大部分时间内扩展，从而大大降低噪声幅度。
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