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131.发明申请公开(公告)号：US20130156148A1
公开(公告)日：2013-06-20
申请号：US13819046
申请日：2011-08-31
CPC分类号： H03K3/02 , G09G3/3677 , G09G2310/0286 , G11C19/184 , G11C19/28
摘要： A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initialization section controlling the discharge section and the second output section. This makes it possible to realize a shift register capable of performing an all-ON operation regardless of clock signals.
摘要翻译： 本发明的触发器包括：输入端子; 输出端子; 第一控制信号端和第二控制信号端; 第一输出部分，包括自举电容器，第一输出部分连接到第一控制信号端子和输出端子; 连接到第一输出部分源和输出端的第二输出部分; 连接到所述输入端子的第一输入部分，所述第一输入部分对所述自举电容器充电; 放电部，使自举电容器放电; 连接到所述输入端子的第二输入部分，所述第二输入部分也连接到所述第二输出部分; 控制所述放电部和所述第二输出部的复位部，所述复位部与所述第二控制信号端子连接; 控制所述第一输出部的第一初始化部; 控制所述第一输入部的第二初始化部; 以及控制排出部和第二输出部的第三初始化部。 这使得可以实现无论时钟信号如何执行全导通操作的移位寄存器。
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公开(公告)号：US08457272B2
公开(公告)日：2013-06-04
申请号：US12734218
申请日：2008-08-26
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/06 , G09G2330/08 , G11C19/28
摘要： At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
摘要翻译： 本发明的至少一个实施例是多个单元电路以多级连接，当单元电路同时导通以输出高电平输出信号时，进行正常操作。 当移位寄存器发生故障时，使得由前一级和后级单元电路提供的输出信号同时设置为高电平，故障恢复电路并包括在单元电路中，在至少一个实施例中检测故障。 故障恢复电路向节点提供高电压，从而强制拉下输出信号。 此外，故障恢复电路强制地对另一个节点进行放电，从而释放在电容中累积的电荷。 结果，故障中的移位寄存器可以立即恢复正常运行。 本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。
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公开(公告)号：US08395419B2
公开(公告)日：2013-03-12
申请号：US12734044
申请日：2008-08-26
IPC分类号： H03B1/00
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.
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公开(公告)号：US20120307959A1
公开(公告)日：2012-12-06
申请号：US13571608
申请日：2012-08-10
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US08269714B2
公开(公告)日：2012-09-18
申请号：US12733119
申请日：2008-05-15
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 高层次。 在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。 因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。
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136.发明申请MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE 有权存储装置，具有存储装置的显示装置，用于存储装置的驱动方法和用于显示装置的驱动方法公开(公告)号：US20120179923A1
公开(公告)日：2012-07-12
申请号：US13395739
申请日：2010-03-18
IPC分类号： G06F1/26
CPC分类号： G09G3/3659 , G09G2300/0857 , G09G2310/08 , G09G2320/0219 , G09G2330/022
摘要： A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source (VDD) for supplying a first potential level; a second power source (VSS) for supplying a second potential level, a third power source (GVDD) for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.
摘要翻译： 存储器件可以执行其中提供离散电平以使存储器单元保持逻辑电平的第一操作模式，并且防止由于在第一操作模式中不必要的电源的操作引起的不必要的功耗。 存储器件包括：用于提供第一电位电平的第一电源（VDD）; 用于提供第二电位电平的第二电源（VSS）;用于提供高于离散电平的最高电位的电位的第三电源（GVDD）; 以及用于提供低于所述离散电平的最低电位的电位的第四电源，所述第一和第二电位电平用于提供所述离散电平，当执行所述第一操作时，引起VDD，VSS和GVDD 运行中，第四个电源停止工作。
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公开(公告)号：US20120176388A1
公开(公告)日：2012-07-12
申请号：US13395536
申请日：2010-05-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G5/39
CPC分类号： G09G3/3648 , G02F1/13624 , G09G2300/043 , G09G2300/0819 , G09G2300/0852 , G09G2300/0876 , G09G2310/063 , G09G2310/08 , G09G2320/0219 , G09G2320/0247 , G09G2340/0428
摘要： In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.
摘要翻译： 在存储器液晶显示装置中，提供给CS线（CSL（i））的辅助电容配线信号（CS）的电位在制作栅极线（GL（i））时一度减小（＆Dgr; Vcs） 数据保持期间（T2）中同时有效（周期t4，期间t10），并且保持电容配线信号（CS）的电位恢复到原来的电位，而同时进行栅极线（GL（i）） 并且刷新输出控制线（RC（i））被激活（时段t5，周期t11）。 这减少了闪烁，从而可以提高存储器液晶显示装置的显示质量。
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公开(公告)号：US20120169580A1
公开(公告)日：2012-07-05
申请号：US13395716
申请日：2010-05-18
IPC分类号： G09G3/36
CPC分类号： G09G3/3618 , G09G3/3614 , G09G3/3659 , G09G2300/0823 , G09G2300/0852
摘要： A memory liquid crystal display device includes a transistor (N1), a transistor (N2), a transistor (N3), a transistor (N4), a first storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37a and a CS line CSL(i)) connected to a pixel electrode (7), and a second storage capacitor (storage capacitor of an overlapping part of a capacitor electrode 37b and a CS extension section 10bb) connected to the pixel electrode (7) via the transistor (N2), the pixel electrode (7) being connected to (a) a source line (SL(j)) via the transistor (N1), (b) a data transfer control line (DT(i)) via the transistor (N4) and the third transistor, (c) a drain electrode (9a) of the transistor (N1) via a contact hole (13), and (d) a source electrode (8b) of the transistor (N2) and to a drain electrode (9c) of the transistor (N4), via a contact hole (14). This allows for improving a yield rate and for reducing malfunction caused by noise generated between signal lines, in a memory liquid crystal display device.
摘要翻译： 存储液晶显示装置包括晶体管（N1），晶体管（N2），晶体管（N3），晶体管（N4），第一存储电容器（电容器电极37a的重叠部分的存储电容器和CS 连接到像素电极（7）的线CSL（i））和连接到像素电极（7）的第二存储电容器（电容器电极37b和CS延伸部分10bb的重叠部分的存储电容器） （N2），经由晶体管（N1）与（a）源极线（SL（j））连接的像素电极（7），（b）经由晶体管的数据传输控制线（DT（i） N4）和第三晶体管，（c）经由接触孔（13）的晶体管（N1）的漏电极（9a）和（d）晶体管（N2）的源电极（8b）和漏极 晶体管（N4）的电极（9c）经由接触孔（14）。 这允许在存储器液晶显示装置中提高成品率并减少由信号线之间产生的噪声引起的故障。
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139.发明申请公开(公告)号：US20120169579A1
公开(公告)日：2012-07-05
申请号：US13395549
申请日：2010-05-18
CPC分类号： H01L27/108 , G09G3/3614 , G09G3/3618 , G09G3/3648 , G09G3/3659 , G09G2300/0823 , G09G2300/0852 , G09G2330/021 , G11C11/406 , G11C2211/4067 , H01L27/12
摘要： A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.
摘要翻译： 晶体管（N1）具有连接到字线（Xi（1））的栅极端子和连接到位线（Yj）的第一导电端子。 晶体管（N2）具有连接到字线（Xi（2））的栅极端子和连接到节点（PIX）的第一导电端子。 晶体管（N3）具有连接到节点（MRY）的栅极端子和连接到字线（Xi（2））的第一导电端子。 晶体管（N4）具有连接到字线（Xi（3））的栅极端子，连接到晶体管（N3）的第二导通端子的第一导电端子和连接到节点（PIX）的第二导电端子， 。 在节点（MRY）和参考电位线（RL1）之间以及在第一（VI））之间的节点（PIX）和参考电位线（RL1）之间形成电容器（Ca1），（Cb1） 晶体管（N3）和节点（MRY）的导通端子。
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140.发明申请Shift Register, Display-Driving Circuit, Displaying Panel, And Displaying Device 有权移位寄存器，显示驱动电路，显示面板和显示设备公开(公告)号：US20120092311A1
公开(公告)日：2012-04-19
申请号：US13377855
申请日：2010-03-18
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2310/0245 , G09G2310/0286 , G09G2310/063 , G09G2320/0233 , G09G2330/026 , G09G2330/027 , G11C19/28 , H03K3/356182
摘要： Disclosed is a shift register for use in a display driving circuit that simultaneously selects signal lines, including, in a stage thereof: a flip-flop including an initialization terminal; and a signal generating circuit that receives a simultaneous selection signal and that generates an output signal of the stage by use of an output of the flip-flop, wherein: the output signal of the stage becomes active due to an activation of the simultaneous selection signal so as to be active during a period of the simultaneous selection; the output of the flip-flop is non-active while the initialization terminal, a set terminal, and a reset terminal of the flip-flop; and the initialization terminal of the flip-flop receives the simultaneous selection signal. This shift register makes it possible to downsize various drivers.
摘要翻译： 公开了一种在显示驱动电路中使用的移位寄存器，其同时选择信号线，其中包括：其包括初始化端子的触发器; 以及信号发生电路，其接收同时选择信号，并且通过使用所述触发器的输出来产生所述级的输出信号，其中：所述级的输出信号由于同时选择信号的激活而变为有效 以便在同时选择期间活跃; 触发器的输出在触发器的初始化端子，设定端子和复位端子处于非有效状态; 并且触发器的初始化端子接收同时选择信号。 该移位寄存器使得可以减小各种驱动程序的尺寸。
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