-
公开(公告)号：US20230087576A1
公开(公告)日：2023-03-23
申请号：US17940956
申请日：2022-09-08
Applicant: Rambus Inc.
Inventor： Michael Raymond Miller , Dongyun Lee
IPC: G06F3/06
Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.
-
公开(公告)号：US20230082649A1
公开(公告)日：2023-03-16
申请号：US17931125
申请日：2022-09-11
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Brian S. Leibowitz , Jade M. Kizer , Thomas H. Greer , Akash Bansal
Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
-
公开(公告)号：US20230081231A1
公开(公告)日：2023-03-16
申请号：US17893790
申请日：2022-08-23
Applicant: Rambus Inc.
Inventor： Taeksang SONG , Steven C. WOO , Torsten PARTSCH
IPC: G06F3/06
Abstract: Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.
-
134.发明申请公开(公告)号：US20230075057A1
公开(公告)日：2023-03-09
申请号：US17945863
申请日：2022-09-15
Applicant: Rambus Inc.
Inventor： Frederick A. WARE
IPC: G06F1/3287 , G06F1/3234 , G06F13/16 , G06F1/3293
Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.
-
公开(公告)号：US11579965B2
公开(公告)日：2023-02-14
申请号：US17481246
申请日：2021-09-21
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Craig E. Hampel
Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
-
Patent Agency Ranking
公开(公告)号：US20230028438A1
公开(公告)日：2023-01-26
申请号：US17852272
申请日：2022-06-28
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely Tsern
Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
-
公开(公告)号：US11551741B2
公开(公告)日：2023-01-10
申请号：US17115538
申请日：2020-12-08
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Brent Haukness
IPC: G06F12/00 , G11C11/406 , G06F13/16
Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.
-
138.发明申请公开(公告)号：US20220407750A1
公开(公告)日：2022-12-22
申请号：US17857338
申请日：2022-07-05
Applicant: Rambus Inc.
Inventor： Nanyan Wang
Abstract: A decision-feedback equalizer (DFE) samples an input signal with respect to a gamut of p reference-voltage levels to place the symbol represented by the input signal within a voltage region. The DFE derives a set of tentative decisions for the voltage region, the set excluding at least one of the possible values for the symbol under consideration. A feedback stage then selects a final decision from among the tentative decisions.
-
公开(公告)号：US20220391332A1
公开(公告)日：2022-12-08
申请号：US17852135
申请日：2022-06-28
Applicant: Rambus Inc.
Inventor： Hongzhong ZHENG , Brent HAUKNESS
Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.
-
公开(公告)号：US11520508B2
公开(公告)日：2022-12-06
申请号：US16880244
申请日：2020-05-21
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
-
-
-
-
-
-
-
-
-
Search Results
3867
records
(took 0.036 seconds)
