公开(公告)号：US10699995B2

公开(公告)日：2020-06-30

申请号：US15974857

申请日：2018-05-09

Applicant: Silicon Laboratories Inc.

Inventor： Michael R. May ,  Charles Guo Lin ,  Carlos Briseno-Vidrios

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64

Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.

公开(公告)号：US10693475B1

公开(公告)日：2020-06-23

申请号：US16427837

申请日：2019-05-31

Applicant: Silicon Laboratories Inc.

Inventor： Xue-Mei Gong ,  James D. Barnette

IPC: H03L7/093

Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.

公开(公告)号：US10681586B2

公开(公告)日：2020-06-09

申请号：US16436134

申请日：2019-06-10

Applicant: Redpine Signals, Inc.

Inventor： Govardhan Mattela

IPC: H04L1/18 ,  H04W4/46 ,  H04W28/04 ,  H04W4/029 ,  H04L1/08 ,  H04W4/02 ,  H04W4/90 ,  H04W4/08 ,  H04W4/70 ,  H04W24/08 ,  H04L1/00 ,  H04L29/12 ,  H04W84/18

Abstract: A system for transmission of incident information includes maintaining a table of RSSI values for a plurality of stations. When an incident is detected, the system first sends a broadcast packet with incident information, and next sends a unicast packet to any station below a particular RSSI threshold until the unicast packet is acknowledged or a retransmission interval passes.

公开(公告)号：US10678674B2

公开(公告)日：2020-06-09

申请号：US15623761

申请日：2017-06-15

Applicant: Silicon Laboratories Inc.

Inventor： Lauri Mikael Hintsala

IPC: H04L29/06 ,  H04L29/08 ,  G06F15/16 ,  H04L12/24 ,  G06F11/36

Abstract: A novel system and method for remotely debugging a network device is disclosed. A debug system is used to transmit debug commands over a network to the network device. The network device interprets the debug commands. The processing unit on the network device includes a special debugging mode where it is able to perform special debug operations. This special debugging mode operates at a priority that is lower than that of the network interface so that the network device can still receive network packets while being debugged. The network device also has the ability to generate responses to the debug commands in some embodiments. The concept of wireless debugging can also be applied to multi-core processors as well.

公开(公告)号：US10673688B2

公开(公告)日：2020-06-02

申请号：US16137815

申请日：2018-09-21

Applicant: Silicon Laboratories Inc.

Inventor： Christian Salmony Olsen ,  Jørgen Franck ,  Peter Shorty ,  Anders T. Brandt

IPC: H04L12/24 ,  H04L12/66 ,  H04L12/26

Abstract: A system and method for improving network resiliency is disclosed. The system includes a network having a plurality of network devices and at least one controller. The controller is configured to create various scenes based on the inputs received from the network devices. The controller is also configured to provide alternate instructions to the network devices in the event that the controller is non-functional. The network devices utilize these alternate instructions when attempts to connect the controller are unsuccessful. In this way, the network is able to operate in a limited way even in the absence of the controller.

公开(公告)号：US10659060B2

公开(公告)日：2020-05-19

申请号：US16143717

申请日：2018-09-27

Applicant: Silicon Laboratories Inc.

Inventor： Timothy A. Monk ,  Rajesh Thirugnanam

IPC: H03L7/091 ,  H03L7/093 ,  G04F10/00

Abstract: A spur cancellation circuit receives a target spur frequency indicative of a frequency of a spur to be canceled and supplies a spur cancellation signal based on the frequency. A frequency tracking circuit tracks a change in the frequency of the spur to be canceled based on a change in phase of the spur cancellation signal and generates an updated target spur frequency based on the change in the frequency of the spur.

公开(公告)号：US10659045B2

公开(公告)日：2020-05-19

申请号：US15634716

申请日：2017-06-27

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed M. Elsayed

IPC: G01R31/26 ,  G11C8/08 ,  H01L21/70 ,  H03K17/06 ,  G11C8/00 ,  H03K19/00 ,  H03K19/003 ,  H03K17/16 ,  H03K19/0185

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

公开(公告)号：US10658999B1

公开(公告)日：2020-05-19

申请号：US16506409

申请日：2019-07-09

Applicant: Silicon Laboratories Inc.

Inventor： Essam S. Atalla ,  Ruifeng Sun ,  Mohamed M. Elkholy

IPC: H03H7/38 ,  H03F3/189 ,  H03H7/01

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

公开(公告)号：US10601431B2

公开(公告)日：2020-03-24

申请号：US16022188

申请日：2018-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Aaron J. Caffee ,  Jeffrey L. Sonntag ,  Brian G. Drost ,  Volodymyr Kratyuk

IPC: H03M1/06 ,  G04F10/00 ,  H03K5/24

Abstract: A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.

公开(公告)号：US10587295B1

公开(公告)日：2020-03-10

申请号：US16217494

申请日：2018-12-12

Applicant: SILICON LABORATORIES INC.

Inventor： Terry Lee Dickey ,  Yan Zhou ,  Praveen Vangala

IPC: H04B1/00 ,  H04B7/00 ,  H04B17/00 ,  H04B1/10

Abstract: A wireless receiver including multiple amplifiers coupled in series for amplifying a signal being received, at least one detector that provides a strength indication of the signal being received, multiple AGC schedules each determining a gain reduction schedule for the amplifiers, an AGC schedule selector that selects one of the AGC schedules based on a schedule select input, and an AGC controller that adjusts a gain of at least one of the amplifiers according to a selected AGC schedule based on the strength indication of the signal being received. The AGC schedules may include a first AGC schedule configured for improved SNR performance and a second AGC schedule configured for improved distortion performance. The second AGC schedule may be selected for improved distortion performance when a strong distorting blocker signal is present, and otherwise the first AGC schedule may be selected for better SNR performance.