公开(公告)号：US06801193B2

公开(公告)日：2004-10-05

申请号：US09808143

申请日：2001-03-15

Applicant: Junichi Nakamura ,  Hideya Seki ,  Masatoshi Yonekubo

Inventor： Junichi Nakamura ,  Hideya Seki ,  Masatoshi Yonekubo

IPC: G09G500

CPC classification number: G09G3/3473 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0857 ,  G09G2310/0235 ,  G09G2310/0267 ,  G09G2310/0275

Abstract: A digital drive apparatus has a memory cell array. Each memory cell includes a storage section that stores a supply of data therein and that is capable of keeping output corresponding to the stored data, and a transfer element that is capable of transferring the data to the storage section. The memory cell also has an address terminal that supplies an address signal to the transfer element, a data terminal that is connected with the transfer element and supplies the data to the storage section via the transfer element, and an output terminal that outputs the data stored in the storage section. The memory cell further includes a reset terminal that supplies a reset signal, which sets the output of the storage section to a predetermined state, to the storage section regardless of the data previously stored in the storage section.

Abstract translation: 数字驱动装置具有存储单元阵列。 每个存储单元包括存储部分，其存储其中的数据，并且能够保持与所存储的数据相对应的输出;以及传送元件，其能够将数据传送到存储部。 存储单元还具有向传送元件提供地址信号的地址端子，与传送元件连接并将数据经由传送元件提供给存储部件的数据端子，以及输出存储的数据的输出端子 在存储部分。 存储单元还包括复位端子，其将存储部分的输出设置为预定状态的复位信号提供给存储部分，而不管先前存储在存储部分中的数据。

公开(公告)号：US20040164944A1

公开(公告)日：2004-08-26

申请号：US10790203

申请日：2004-03-02

Inventor： Toshio Miyazawa ,  Tomohiko Sato

IPC: G09G003/36

CPC classification number: G09G3/3659 ,  G09G3/2074 ,  G09G3/3614 ,  G09G2300/0857

Abstract: The invention provides an active matrix type display device which realizes an image display of multiple gray scale exhibiting high numerical aperture and high definition with a least number of wiring by having an image memory circuit equivalent to a static memory circuit without using two voltages, that is, high and low voltages. Pixels are arranged at portions where a plurality of scanning lines (selection signal lines) and a plurality of signal lines (data lines (video signal lines)) intersect each other, each pixel is comprised of a pixel electrode, a switching element which selects the pixel electrode and a memory circuit which stores data to be written in the pixel electrode, and a power supply line which applies an AC voltage to the memory circuit is provided.

Abstract translation: 本发明提供了一种有源矩阵型显示装置，其通过具有与静态存储电路相当的图像存储电路而实现具有最小数量布线的高数值孔径和高清晰度的多灰度图像显示，而不使用两个电压，也就是说 ，高低电压。 像素布置在多个扫描线（选择信号线）和多个信号线（数据线（视频信号线））相交的部分处，每个像素包括像素电极，选择 像素电极和存储要写入像素电极的数据的存储电路，以及向存储电路施加AC电压的电源线。

公开(公告)号：US06771247B2

公开(公告)日：2004-08-03

申请号：US09812571

申请日：2001-03-21

Applicant: Hajime Sato ,  Hiroyuki Kimura ,  Takashi Maeda ,  Takanori Tsunashima

Inventor： Hajime Sato ,  Hiroyuki Kimura ,  Takashi Maeda ,  Takanori Tsunashima

IPC: G09G336

CPC classification number: G09G3/3659 ,  G02F1/136 ,  G09G2300/0857 ,  G09G2320/10 ,  G09G2330/021

Abstract: A display has display pixels provided with digital memories, respectively. In each display pixel, a pixel electrode and a data line are connected to each other through a first switch, and the pixel electrode and the digital memory are connected to each other through a second switch. In a first display period, the second switches are turned off and the first switches are turned on, to display video data supplied from the data lines. In a second display period, the second switches are turned on and the first switches are turned off, to stop scan and data drivers and display video data stored in the digital memories.

Abstract translation: 显示器分别具有设置有数字存储器的显示像素。 在每个显示像素中，像素电极和数据线通过第一开关彼此连接，并且像素电极和数字存储器通过第二开关相互连接。 在第一显示周期中，第二开关断开，第一开关导通，以显示从数据线提供的视频数据。 在第二显示期间，第二开关导通，第一开关断开，停止扫描和数据驱动并显示数字存储器中存储的视频数据。

公开(公告)号：US20040125090A1

公开(公告)日：2004-07-01

申请号：US10329645

申请日：2002-12-26

Applicant: eLCOS Microdisplay Technology, Inc.

Inventor： Edwin Lyle Hudson

IPC: G09G005/00

CPC classification number: H04N9/312 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2300/0857 ,  G09G2320/0204 ,  G09G2320/0247

Abstract: The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

Abstract translation: 本发明公开了一种通过在每个像素控制电路中设置电压控制器来控制输入到像素电极的电压的像素显示配置。 该控制器包括将输入到像素电极的电压复用的功能以及位缓冲和去耦功能，以将输入电压电平去耦和灵活地改变到像素电极。 直流平衡的速率可以提高到1KHz及更高​​，以减轻直流偏移效应的可能性和由直流平衡速率慢引起的图像残留问题。 本发明还公开了一种从一个DC平衡状态切换到另一个直流平衡状态而不将数据重写到面板上的使能技术。 因此，不需要实施高压CMOS设计，并且可以应用标准CMOS技术来制造用于LCOS显示器的存储单元和控制面板，具有较低的生产成本和更高的产量。

公开(公告)号：US20040066358A1

公开(公告)日：2004-04-08

申请号：US10656299

申请日：2003-09-08

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takaji Numao

IPC: G09G003/30

CPC classification number: G09G3/2011 ,  G09G3/2022 ,  G09G3/2081 ,  G09G3/3233 ,  G09G3/3291 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0857 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2320/0266 ,  G09G2320/029 ,  G09G2320/0626 ,  G09G2330/02 ,  G09G2360/148

Abstract: A current driver circuit in a driver circuit generates, and maintains, a state where a drive current for an electro-optic device flows through a current output TFT and a capacitor, using a constant current output from a single constant current source during a non-drive controllable period for the pixel. The driver circuit performs the previous operation on each pixel. The current driver circuit then generates the drive current in the maintained circuit state and passes the drive current through a source line to the pixel which is in a drive controllable period by means of voltage state of the gate line, so as to control the driving of the pixel. Thus, in the pixel receiving the drive current, the drive current flows through the electro-optic device to effect a display. The current driver circuit for the electro-optic device is capable of inhibiting the current value from varying from one source line to another, while permitting construction based on a low temperature polysilicon TFT or CG silicon TFT.

Abstract translation: 驱动电路中的电流驱动电路通过使用从单个恒定电流源输出的恒定电流产生并维持电光装置的驱动电流流过电流输出TFT和电容器的状态， 驱动可控周期的像素。 驱动电路对每个像素执行先前的操作。 当前的驱动电路然后产生维持电路状态的驱动电流，并通过栅极线的电压状态将驱动电流通过源极线传递到处于驱动可控周期的像素，以便控制驱动电流 像素。 因此，在接收驱动电流的像素中，驱动电流流过电光装置进行显示。 用于电光器件的电流驱动电路能够抑制电流值从一个源极线变化到另一个源极线，同时允许基于低温多晶硅TFT或CG硅TFT的结构。

公开(公告)号：US06671023B2

公开(公告)日：2003-12-30

申请号：US10003686

申请日：2001-12-06

Applicant: Yusuke Tsutsui ,  Ryoichi Yokoyama ,  Takeo Yoshimura

Inventor： Yusuke Tsutsui ,  Ryoichi Yokoyama ,  Takeo Yoshimura

IPC: G02F11343

CPC classification number: G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2300/0857 ,  G09G2330/022 ,  G09G2340/0421

Abstract: The active matrix display device of this invention operates under two operation modes: a normal operation mode in which the pixel element electrode sequentially receives the pixel element voltage in response to an image signal sequentially inputted and a memory operation mode in which display is made based on the data held by the retaining circuit. In this active matrix display device, at least a part of the retaining circuit is set for the predetermined voltage and functions as a storage capacitance element for holding the voltage between the pixel element electrode and the common electrode under the normal operation mode. In this configuration, it is possible to reduce the size of the storage capacitance element originally disposed, because at least a part of the retaining circuit works as the storage capacitance element. Therefore, as the size of the storage capacitance element gets smaller, the size of the pixel element can also be smaller, leading to the size reduction of the device as a whole.

公开(公告)号：US06646654B2

公开(公告)日：2003-11-11

申请号：US09838380

申请日：2001-04-20

Applicant: Yuichi Takagi

Inventor： Yuichi Takagi

IPC: G09G510

CPC classification number: G09G3/3283 ,  G09G3/2014 ,  G09G3/2085 ,  G09G3/3233 ,  G09G2300/0857 ,  G09G2320/0247

Abstract: A modulation circuit capable of high resolution pulse width modulation while keeping down the bit length and an image display provided with the modulation circuit. By the A/D converter 4, the video signal Sv converted into a binary code having a preset bit length is divided into a plurality of binary codes by the controller 3 from the most significant bit to the least significant bit. Corresponding to the thus obtained plurality of divided binary codes, serial data is generated for producing a pulse current of a pulse width and current value according to the value of the binary code and is output to pulse width modulation circuits 1 cascade connected to the controller 3. The pulse width modulation circuits supply LEDs 3 of the pixels pulse currents of pulse widths and current values corresponding to the serial data.

公开(公告)号：US20030201986A1

公开(公告)日：2003-10-30

申请号：US10134935

申请日：2002-04-30

Inventor： Thomas E. Willis ,  Michael O'Connor

IPC: G09G005/00

CPC classification number: G09G3/2014 ,  G09G3/3648 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0857 ,  G09G2310/0259

Abstract: An array of display elements (e.g., pixels) in a display device (e.g., a spatial light modulator) may be digitally driven using pulse width modulated waveforms. Pulse width modulated waveforms may be locally generated to controllably drive each pixel in display systems with digital storage. A pixel drive circuit having a waveform generator may receive first digital data indicative of an optical output from an associated first display element. Moreover, second digital data indicative of a common reference with respect to a second display element may also be received at the first display element for comparison purposes. As a result, in one embodiment, a pulse width modulated waveform that includes only a single transition separating a first pulse interval and a second pulse interval may be generated based on a pixel value and a global count value instead of relying upon adding up multiple non-overlapping waveforms to drive a pixel.

Abstract translation: 显示装置（例如，空间光调制器）中的显示元件阵列（例如，像素）可以使用脉冲宽度调制波形进行数字驱动。 脉冲宽度调制波形可以在本地产生，以可控地驱动具有数字存储的显示系统中的每个像素。 具有波形发生器的像素驱动电路可以从相关联的第一显示元件接收指示光输出的第一数字数据。 此外，为了比较的目的，还可以在第一显示元件处接收指示相对于第二显示元件的公共参考的第二数字数据。 结果，在一个实施例中，可以基于像素值和全局计数值来生成仅包括分离第一脉冲间隔和第二脉冲间隔的单个转变的脉宽调制波形，而不是依赖于将多个非零 - 重叠波形来驱动像素。

公开(公告)号：US20030174116A1

公开(公告)日：2003-09-18

申请号：US10325937

申请日：2002-12-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takashi Maeda ,  Takanori Tsunashima ,  Hiroyuki Kimura

IPC: G09G003/36

CPC classification number: G09G3/3659 ,  G09G2300/0809 ,  G09G2300/0857

Abstract: During a still picture display period, a normal write voltage is sometimes unable to be applied to a liquid crystal layer 16 because two memory switch elements 21 and 22 are simultaneously turned on, and the output and the inverted output from the digital memory 18 are applied simultaneously to a pixel electrode 13. According to the present invention, the pulse width for the on period of one of the memory switch elements 21 and 22 is narrower than the pulse width for the off period of the other memory switch element, so that the on periods of the two memory switch elements 21 and 22 do not overlap. In this manner, the memory switch elements 21 and 22 are prevented from being turned on at the same time.

Abstract translation: 在静止图像显示期间，由于两个存储器开关元件21和22同时导通，所以正常的写入电压有时不能施加到液晶层16，并且应用来自数字存储器18的输出和反相输出 根据本发明，一个存储开关元件21和22的导通周期的脉冲宽度比另一个存储器开关元件的截止周期的脉冲宽度窄，因此， 两个存储开关元件21和22的周期不重叠。 以这种方式，防止存储器开关元件21和22同时导通。

公开(公告)号：US06580657B2

公开(公告)日：2003-06-17

申请号：US09754489

申请日：2001-01-04

Applicant: James Lawrence Sanford ,  Eugene S. Schlig

Inventor： James Lawrence Sanford ,  Eugene S. Schlig

IPC: G11C800

CPC classification number: G09G3/3233 ,  G09G3/006 ,  G09G3/2014 ,  G09G3/3291 ,  G09G2300/0809 ,  G09G2300/0857 ,  G09G2300/0861 ,  G09G2310/0254 ,  G09G2310/0256 ,  G09G2310/063 ,  G09G2320/0233 ,  G09G2320/043 ,  G09G2320/046 ,  G09G2320/0626 ,  G09G2320/0633 ,  G09G2320/064 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2330/04 ,  G11C11/419 ,  H01L27/32

Abstract: A pixel circuit comprises an organic light emitting diode (OLED), and a static memory for storing data that represents an operational state of the OLED. In alternative embodiments, a pixel circuit may include a complementary metal oxide semiconductor (CMOS) circuit for controlling the OLED, a protection circuit for protecting the CMOS circuit from an over-voltage condition, and a current source with a field effect transistor (FET) having a static gate to source voltage that is greater than a threshold voltage of the FET.