-
公开(公告)号：US20220385320A1
公开(公告)日：2022-12-01
申请号：US17742679
申请日：2022-05-12
Applicant: Rambus Inc.
Inventor： Panduka Wijetunga
Abstract: A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.
-
公开(公告)号：US20220382691A1
公开(公告)日：2022-12-01
申请号：US17830838
申请日：2022-06-02
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Kenneth Lee Wright
Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.
-
公开(公告)号：US20220374306A1
公开(公告)日：2022-11-24
申请号：US17840153
申请日：2022-06-14
Applicant: Rambus Inc.
Inventor： Angus William McLAREN , Robert A. HEATON , Aaron ALI , Frederick A. WARE
Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.
-
公开(公告)号：US20220365552A1
公开(公告)日：2022-11-17
申请号：US17830163
申请日：2022-06-01
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
公开(公告)号：US11501848B2
公开(公告)日：2022-11-15
申请号：US17344155
申请日：2021-06-10
Applicant: Rambus Inc.
Inventor： Adrian E. Ong , Fan Ho
IPC: G11C29/04 , G11C29/00 , G11C29/44 , G11C29/48 , G11C11/401 , G11C29/12 , G11C11/408 , G11C29/02
Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
-
Patent Agency Ranking
公开(公告)号：US11500986B2
公开(公告)日：2022-11-15
申请号：US17028831
申请日：2020-09-22
Applicant: Rambus Inc.
Inventor： Simon Hoerder
IPC: G06F21/55
Abstract: A masked logic gate protected against side-channel attacks using Boolean masking with d+1 shares for each input variable, where d is an integer at least equal to 1 representing the protection order is described. The masked logic gate includes a first input configured to receive a number of shares yj (j=0, 1, 2 . . . ); a second input configured to receive (d+1)2 shares xi (i=0, 1, 2 . . . ) representative of an intermediate result output by one layer of a tree of gates implementing low-latency masking with a protection order of d; and a (d+1)-share output obtained by applying a logic function of the masked logic gate to the shares of the first and second inputs using domain-oriented masking.
-
公开(公告)号：US20220358989A1
公开(公告)日：2022-11-10
申请号：US17725026
申请日：2022-04-20
Applicant: Rambus Inc.
Inventor： Panduka Wijetunga , Aws Shallal , Joey M. Esteves
IPC: G11C11/4074
Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.
-
公开(公告)号：US11488018B1
公开(公告)日：2022-11-01
申请号：US16908024
申请日：2020-06-22
Applicant: Rambus Inc.
Inventor： Steven C. Woo
Abstract: One or more neural network layers are implemented by respective sets of signed multiply-accumulate units that generate dual analog result signals indicative of positive and negative product accumulations, respectively. The two analog result signals and thus the positive and negative product accumulations are differentially combined to produce a merged analog output signal that constitutes the output of a neural node within the subject neural network layer.
-
公开(公告)号：US11487676B2
公开(公告)日：2022-11-01
申请号：US16953230
申请日：2020-11-19
Applicant: Rambus Inc.
Inventor： Hongzhong Zheng , James Tringali
IPC: G06F12/1036 , G06F12/02
Abstract: A memory system includes an address mapping circuit. The address mapping circuit receives an input memory address having a first set of address bits. The address mapping circuit applies a logic function to the input memory address to generate a mapped memory address. The logic function uses at least a subset of the first set of address bits in two separate operations that respectively determine two portions of the mapped memory address.
-
公开(公告)号：US20220343956A1
公开(公告)日：2022-10-27
申请号：US17705039
申请日：2022-03-25
Applicant: Rambus Inc.
Inventor： Ian P. Shaeffer , Bret Stott , Benedict C. Lau
Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
-
-
-
-
-
-
-
-
-
Search Results
3867
records
(took 0.038 seconds)
