公开(公告)号：US07075841B2

公开(公告)日：2006-07-11

申请号：US10870694

申请日：2004-06-16

申请人： Claudio Resta ,  Ferdinando Bedeschi ,  Fabio Pellizzer ,  Giulio Casagrande

发明人： Claudio Resta ,  Ferdinando Bedeschi ,  Fabio Pellizzer ,  Giulio Casagrande

IPC分类号： G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.

摘要翻译： 一种相变型存储器件，其中存储器单元具有可在存储器单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件。 写入级连接到存储单元，并且具有被配置为产生没有恒定部分的放电电流并使存储器单元改变状态的电容电路。

公开(公告)号：US20060049392A1

公开(公告)日：2006-03-09

申请号：US11264084

申请日：2005-11-01

申请人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

发明人： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

IPC分类号： H01L29/06

CPC分类号： H01L29/685 ,  H01L27/101 ,  H01L27/24

摘要： A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

公开(公告)号：US20060018183A1

公开(公告)日：2006-01-26

申请号：US10970842

申请日：2004-10-20

申请人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

发明人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： G11C8/02

CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

摘要翻译： 一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置 用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。 非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。

公开(公告)号：US06974734B2

公开(公告)日：2005-12-13

申请号：US10758289

申请日：2004-01-15

申请人： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

发明人： Fabio Pellizzer ,  Roberto Bez ,  Marina Tosi

IPC分类号： H01L21/8238 ,  H01L27/24 ,  H01L21/338 ,  H01L29/94

CPC分类号： H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A process wherein an insulating region is formed in a body at least around an array portion of a semiconductor body; a gate electrode of semiconductor material is formed on top of a circuitry portion of the semiconductor body; a first silicide protection mask is formed on top of the array portion; the gate electrode and the active areas of the circuitry portion are silicided and the first silicide protection mask is removed. The first silicide protection mask (is of polysilicon and is formed simultaneously with the gate electrode. A second silicide protection mask of dielectric material covering the first silicide protection mask is formed before silicidation of the gate electrode. The second silicide protection mask is formed simultaneously with spacers formed laterally to the gate electrode.

摘要翻译： 一种绝缘区域至少在半导体本体的阵列部分周围形成在主体中的工艺; 半导体材料的栅电极形成在半导体本体的电路部分的顶部; 在阵列部分的顶部形成第一硅化物保护掩模; 栅电极和电路部分的有源区被硅化，并且去除第一硅化物保护掩模。 第一硅化物保护掩模（多晶硅，并与栅电极同时形成）在栅极电极硅化之前形成覆盖第一硅化物保护掩模的第二硅化物保护掩模，第二硅化物保护掩膜与 间隔件横向形成到栅电极。

公开(公告)号：US20050255665A1

公开(公告)日：2005-11-17

申请号：US11156989

申请日：2005-06-20

申请人： Fabio Pellizzer ,  Agostino Pirovano

发明人： Fabio Pellizzer ,  Agostino Pirovano

IPC分类号： G11C11/56 ,  H01L21/76 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： The method forms a phase change memory cell with a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

摘要翻译： 该方法形成具有电阻元件和相变材料的存储区域的相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区具有第二薄部，所述第二薄部在与所述第一方向横切的第二方向上具有第二亚光刻尺寸。 第一和第二薄部分是直接电接触并限定具有亚光刻范围的接触区域。 第二薄部分形成在亚光刻尺寸的狭缝中。 根据第一种解决方案，氧化物间隔物部分形成在由模具层限定的光刻开口中。 根据不同的解决方案，牺牲区域形成在模具层的顶部上，并用于在模具层中形成亚光刻缝。

公开(公告)号：US06816404B2

公开(公告)日：2004-11-09

申请号：US10319439

申请日：2002-12-12

申请人： Osama Khouri ,  Ferdinando Bedeschi ,  Giorgio Bosisio ,  Fabio Pellizzer

发明人： Osama Khouri ,  Ferdinando Bedeschi ,  Giorgio Bosisio ,  Fabio Pellizzer

IPC分类号： G11C700

CPC分类号： G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

摘要翻译： 相变非易失性存储器阵列由在彼此正交的第一和第二方向上延伸的多个存储单元形成。 多个列选择线平行于第一方向延伸。 多个字选择线平行于第二方向延伸。 每个存储单元包括PCM存储元件和选择晶体管。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线。 PCM存储元件的第二端子连接到相应的列选择线，并且在读取和编程存储器单元的同时，选择晶体管的第二端子连接到参考电位区域。