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    Systems and methods for erasing charge-trap flash memory
    1.
    发明授权
    Systems and methods for erasing charge-trap flash memory 有权
    擦除电荷陷阱闪存的系统和方法

    公开(公告)号：US08611158B2

    公开(公告)日：2013-12-17

    申请号：US13220883

    申请日：2011-08-30

    申请人： Diego Della Mina ,  Chiara Missiroli ,  Osama Khouri

    发明人： Diego Della Mina ,  Chiara Missiroli ,  Osama Khouri

    IPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/06

    CPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/3445 ,  H01L27/1157

    摘要： FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.

    摘要翻译： FLASH存储器件至少包含一个存储器堆栈。 晶体管堆叠包括第一（或源极）选择晶体管，第二（或漏极）选择晶体管和串联连接的多个存储单元晶体管。 在擦除操作期间，第一和第二选择器晶体管中的每一个具有施加的偏置，从而将选择晶体管从电浮动状态释放，同时偏置每个存储单元晶体管。

    Method of transferring data in an electrically programmable memory
    3.
    发明授权
    Method of transferring data in an electrically programmable memory 有权
    在电可编程存储器中传送数据的方法

    公开(公告)号：US07471576B2

    公开(公告)日：2008-12-30

    申请号：US11931497

    申请日：2007-10-31

    申请人： Osama Khouri ,  Stefano Zanardi ,  Giulio Martinozzi

    发明人： Osama Khouri ,  Stefano Zanardi ,  Giulio Martinozzi

    IPC分类号： G11C7/10 ,  G11C11/34 ,  G11C16/04 ,  G11C8/00

    CPC分类号： G11C16/26

    摘要： A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

    摘要翻译： 提供了一种用于在包括形成存储器页面的存储器单元的存储器中传送数据的方法，以及包括寄存器的页缓冲器，其中信号线选择性地将存储在寄存器中的数据传送到所选择的一个存储器页的存储器单元， 存储器的输出接口。 从存储器页面选择的一个存储器单元的存储单元中读取或写入的数据至少暂时存储在寄存器中，缓冲寄存器的输出，以使寄存器的输出与信号线分离。 信号线包括各自耦合到耦合到存储器的输出接口的一些存储器单元和数据线的位线。 缓冲包括根据存储在寄存器中的数据字选择性地驱动位线或数据线。

    METHOD OF TRANSFERRING DATA IN AN ELECTRICALLY PROGRAMMABLE MEMORY
    4.
    发明申请
    METHOD OF TRANSFERRING DATA IN AN ELECTRICALLY PROGRAMMABLE MEMORY 有权
    在电子可编程存储器中传输数据的方法

    公开(公告)号：US20080065823A1

    公开(公告)日：2008-03-13

    申请号：US11931497

    申请日：2007-10-31

    申请人： OSAMA KHOURI ,  Stefano Zanardi ,  Giulio Martinozzi

    发明人： OSAMA KHOURI ,  Stefano Zanardi ,  Giulio Martinozzi

    IPC分类号： G06F12/00

    CPC分类号： G11C16/26

    摘要： A method is provided for transferring data in a memory that includes memory cells forming memory pages, and a page buffer that includes a register, with signal lines selectively transferring data stored in the register to the memory cells of a selected one of the memory pages and an output interface of the memory. Data read from or to be written to the memory cells of the selected one of the memory pages is at least temporarily stored in the register, and outputs of the register are buffered so as to decouple the outputs of the register from the signal lines. The signal lines include bitlines that are each coupled to some of the memory cells and data lines that are coupled to the output interface of the memory. The buffering comprises selectively driving the bitlines or the data lines according to a data word that is stored in the register.

    摘要翻译： 提供了一种用于在包括形成存储器页面的存储器单元的存储器中传送数据的方法，以及包括寄存器的页缓冲器，其中信号线选择性地将存储在寄存器中的数据传送到所选择的一个存储器页的存储器单元， 存储器的输出接口。 从存储器页面选择的一个存储器单元的存储单元中读取或写入的数据至少暂时存储在寄存器中，缓冲寄存器的输出，以使寄存器的输出与信号线分离。 信号线包括各自耦合到耦合到存储器的输出接口的一些存储器单元和数据线的位线。 缓冲包括根据存储在寄存器中的数据字选择性地驱动位线或数据线。

    Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell
    6.
    发明申请
    Electronic memory device having high density non-volatile memory cells and a reduced capacitive interference cell-to-cell 有权
    具有高密度非易失性存储单元的电子存储器件和减小的电容干扰单元到单元

    公开(公告)号：US20060158931A1

    公开(公告)日：2006-07-20

    申请号：US11300053

    申请日：2005-12-14

    申请人： Osama Khouri ,  Carlo Caimi ,  Giovanni Mastrodomenico ,  Paolo Caprara

    发明人： Osama Khouri ,  Carlo Caimi ,  Giovanni Mastrodomenico ,  Paolo Caprara

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115

    摘要： An electronic memory device with a high density of non-volatile memory cells has a reduced capacitance cell-to-cell interference. The memory cells are integrated on a semiconductor substrate and are organized in a matrix of cells with word lines and bit lines connected to the cells. Each memory cell includes at least one floating gate transistor having a floating gate region projecting from the substrate, and a control gate region capacitively coupled to the floating gate region. Between the cells of opposite word lines, a lateral coating is provided that includes at least one conductive layer floating along the direction of the bit lines.

    摘要翻译： 具有高密度非易失性存储单元的电子存储器件具有减小的电容单元间干扰。 存储单元被集成在半导体衬底上，并被组织成具有连接到单元的字线和位线的单元矩阵。 每个存储单元包括至少一个浮置栅极晶体管，其具有从衬底突出的浮置栅极区域和与该浮动栅极区域电容耦合的控制栅极区域。 在相对字线的单元之间，提供横向涂层，其包括沿着位线的方向浮动的至少一个导电层。

    Method of writing to a phase change memory device
    7.
    发明申请
    Method of writing to a phase change memory device 有权
    写入相变存储器件的方法

    公开(公告)号：US20060126381A1

    公开(公告)日：2006-06-15

    申请号：US11350300

    申请日：2006-02-07

    申请人： Osama Khouri ,  Claudio Resta

    发明人： Osama Khouri ,  Claudio Resta

    IPC分类号： G11C11/00 ,  G11C7/10

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

    摘要： A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

    摘要翻译： 相变存储器具有由多个单元形成的阵列，每个单元包括煅烧材料的存储元件和与存储元件串联连接的选择元件; 连接到所述单元的多个地址线; 连接到阵列的写阶段和阅读阶段。 写入级由电流发生器形成，电流发生器向所选择的单元提供预设电流，以便改变存储元件的电阻。 读取通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较来进行电压。

    Charge pump circuit with a brief settling time and high output voltage regulation precision
    8.
    发明申请
    Charge pump circuit with a brief settling time and high output voltage regulation precision 有权
    电荷泵电路具有短暂的稳定时间和高输出电压调节精度

    公开(公告)号：US20050127982A1

    公开(公告)日：2005-06-16

    申请号：US10982528

    申请日：2004-11-05

    申请人： Osama Khouri ,  Giancarlo Ragone

    发明人： Osama Khouri ,  Giancarlo Ragone

    IPC分类号： G05F1/10 ,  H02M3/07

    CPC分类号： H02M3/073

    摘要： A circuit for converting a direct current input voltage into an output voltage greater than the input voltage. The circuit includes a charge pump and a block for generating pulse signals of a predetermined frequency to be applied to a control input of the charge pump. The settling time, i.e. the time necessary for the output voltage to attain its operating value and to maintain it with a given precision, is reduced by providing the circuit with charge injection control via modulation of the duty cycle of the pulse signals as a function of the difference between the output voltage, or a predetermined fraction thereof, and a predetermined reference voltage and in such a manner as to reduce the settling time as the difference diminishes. The circuit includes a regulator that controls the charge pump based upon the predetermined reference voltage.

    摘要翻译： 用于将直流输入电压转换成大于输入电压的输出电压的电路。 该电路包括一个电荷泵和用于产生预定频率的脉冲信号以供应给电荷泵的控制输入的块。 通过调节脉冲信号的占空比来调节电路的电荷注入控制，降低了稳定时间，即输出电压达到其工作值并保持给定精度所需的时间，作为 输出电压或其预定分数之间的差异与预定参考电压之间的差异，并且以随着差异减小而减小稳定时间的方式。 电路包括基于预定参考电压来控制电荷泵的调节器。

    Programmable voltage generator
    9.
    发明授权
    Programmable voltage generator 有权
    可编程电压发生器

    公开(公告)号：US06650173B1

    公开(公告)日：2003-11-18

    申请号：US09714852

    申请日：2000-11-15

    申请人： Osama Khouri ,  Rino Micheloni ,  Andrea Sacco ,  Guido Torelli

    发明人： Osama Khouri ,  Rino Micheloni ,  Andrea Sacco ,  Guido Torelli

    IPC分类号： G05F110

    CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/56 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/5004

    摘要： The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

    摘要翻译： 电压发生器包括负反馈回路，其包括具有反馈节点的可编程分压器。 分压器包括设置在电压发生器的输出端和反馈节点之间并具有可变电阻的可编程电阻器。 可编程电阻器包括固定电阻器和彼此串联布置并且限定多个中间节点的多个附加电阻器。 附加电阻器可以通过设置在电压发生器的输出端和各个中间节点之间的开关选择性地连接，以便根据提供给开关的命令信号来定义可编程的输出电压V0。

    Single supply voltage nonvolatile memory device with row decoding
    10.
    发明授权
    Single supply voltage nonvolatile memory device with row decoding 有权
    单电源电压非易失性存储器件，具有行解码功能

    公开(公告)号：US06373780B1

    公开(公告)日：2002-04-16

    申请号：US09627273

    申请日：2000-07-28

    申请人： Rino Micheloni ,  Osama Khouri ,  Andrea Sacco ,  Massimiliano Picca

    发明人： Rino Micheloni ,  Osama Khouri ,  Andrea Sacco ,  Massimiliano Picca

    IPC分类号： G11C800

    CPC分类号： G11C5/145 ,  G11C5/14 ,  G11C8/10

    摘要： The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.

    摘要翻译： 存储器件包括具有包括全局字线和本地字线的组织的存储器阵列，寻址全局字线的全局行解码器，寻址本地字线的本地行解码器，提供全局字线的全局电源级 行解码器，以及供应本地行解码器的本地电源级。