公开(公告)号：US20070235806A1

公开(公告)日：2007-10-11

申请号：US11279063

申请日：2006-04-07

申请人： Rajiv Joshi ,  Louis Hsu ,  Oleg Gluschenkov

发明人： Rajiv Joshi ,  Louis Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US07271049B2

公开(公告)日：2007-09-18

申请号：US11514605

申请日：2006-09-01

申请人： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

发明人： Oleg Gluschenkov ,  Jack A. Mandelman ,  Michael P. Belyansky ,  Bruce B. Doris

IPC分类号： H01L21/8238

CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

公开(公告)号：US07253482B2

公开(公告)日：2007-08-07

申请号：US11161447

申请日：2005-08-03

申请人： Huilong Zhu ,  Oleg Gluschenkov

发明人： Huilong Zhu ,  Oleg Gluschenkov

IPC分类号： H01L29/76

CPC分类号： H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/7624 ,  H01L29/66659 ,  H01L29/7835

摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.

摘要翻译： 场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域 仅沿着栅极导体的宽度的选定位置。

公开(公告)号：US07247547B2

公开(公告)日：2007-07-24

申请号：US10905454

申请日：2005-01-05

申请人： Huilong Zhu ,  Oleg Gluschenkov ,  Chun-Yung Sung

发明人： Huilong Zhu ,  Oleg Gluschenkov ,  Chun-Yung Sung

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/26506 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.

摘要翻译： 提供一种形成场效应晶体管的方法，其包括从单晶半导体区域形成具有第一深度的非晶化半导体区域，随后在非晶化半导体区域的沟道部分的上方形成第一栅极导体。 然后将包括n型掺杂剂和p型掺杂剂中的至少一种的第一掺杂剂注入第二深度到不被第一栅极导体掩蔽的非晶化半导体区域的部分，以形成与沟道相邻的源极/漏极部分 一部分。 然后将衬底加热以使非晶化半导体区域的沟道部分和源极/漏极部分重结晶。 在加热步骤之后，至少部分重结晶的半导体区域被局部加热以在沟道部分和源极/漏极部分中的至少一个中激活掺杂剂。

公开(公告)号：US20070164768A1

公开(公告)日：2007-07-19

申请号：US11306985

申请日：2006-01-18

申请人： Louis Hsu ,  Hayden Cranford ,  Oleg Gluschenkov ,  James Mason ,  Michael Sorna ,  Chih-Chao Yang

发明人： Louis Hsu ,  Hayden Cranford ,  Oleg Gluschenkov ,  James Mason ,  Michael Sorna ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  G01R31/318533

摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.

摘要翻译： 提供一种封装的半导体芯片，其包括半导体芯片和封装元件。 半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。 封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。 半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。 半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间，将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时 被监测元件的电阻超过阈值。

公开(公告)号：US20070007601A1

公开(公告)日：2007-01-11

申请号：US11509866

申请日：2006-08-25

申请人： Louis Hsu ,  Oleg Gluschenkov ,  Jack Mandelman ,  Carl Radens

发明人： Louis Hsu ,  Oleg Gluschenkov ,  Jack Mandelman ,  Carl Radens

IPC分类号： H01L21/8244 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

摘要翻译： 形成SRAM单元装置的方法包括以下步骤。 形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。 通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到 到共同的身体层。 形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。 然后，连接FET晶体管以形成SRAM单元。

公开(公告)号：US20060145274A1

公开(公告)日：2006-07-06

申请号：US11365502

申请日：2006-03-02

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L29/94

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

公开(公告)号：US20060131659A1

公开(公告)日：2006-06-22

申请号：US11318844

申请日：2005-12-27

申请人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

IPC分类号： H01L29/94

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

公开(公告)号：US20060099783A1

公开(公告)日：2006-05-11

申请号：US10904391

申请日：2004-11-08

申请人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

发明人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

IPC分类号： H01L21/3205

CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located atop a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区，其包括位于半导体衬底的表面上方的栅极导体; 以及与栅极导体自对准的低k电介质材料。

公开(公告)号：US07026247B2

公开(公告)日：2006-04-11

申请号：US10696686

申请日：2003-10-28

申请人： Omer H. Dokumaci ,  Oleg Gluschenkov

发明人： Omer H. Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L21/461

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/82385 ,  Y10S438/947

摘要： A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.

摘要翻译： 提供了用于制造微结构的自校正蚀刻（SCORE）工艺。 本发明的SCORE方法对于降低硬掩模的预选特征而不降低每个晶片内的临界尺寸（CD）的变化特别有用。 或者，通过应用SCORE可以显着地减少在打印期间产生的硬掩模特征的CD变化。 因此，可以可靠地制造超亚光刻特征（例如，纳米结构）。 因此，本发明的方法可以用于提高电路性能，同时提高制造成品率。