利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

208 条记录 (耗时 0.018 秒)

    Strained Si on multiple materials for bulk or SOI substrates
    2.
    发明申请
    Strained Si on multiple materials for bulk or SOI substrates 有权
    应变Si在多种材料上用于体或SOI衬底

    公开(公告)号：US20050269561A1

    公开(公告)日：2005-12-08

    申请号：US10859736

    申请日：2004-06-03

    申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

    发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

    IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

    摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

    摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。

    NFETs using gate induced stress modulation
    3.
    发明申请
    NFETs using gate induced stress modulation 失效
    使用栅极诱导应力调制的NFET

    公开(公告)号：US20050064646A1

    公开(公告)日：2005-03-24

    申请号：US10667601

    申请日：2003-09-23

    申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

    发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

    摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

    摘要翻译： 一种用于制造集成电路的方法，该集成电路包括通过用掩模覆盖p型场效应晶体管的多个半导体器件，包括n型场效应晶体管和p型场效应晶体管，并且氧化栅极多晶硅的一部分 的n型场效应晶体管，使得在n型场效应晶体管的沟道内形成拉伸机械应力。

    STRAINED Si ON MULTIPLE MATERIALS FOR BULK OR SOI SUBSTRATES
    6.
    发明申请
    STRAINED Si ON MULTIPLE MATERIALS FOR BULK OR SOI SUBSTRATES 失效
    用于大块或SOI衬底的多种材料上的应变Si

    公开(公告)号：US20070166897A1

    公开(公告)日：2007-07-19

    申请号：US11694373

    申请日：2007-03-30

    申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

    发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Huilong Zhu

    IPC分类号： H01L21/84

    CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054

    摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.

    摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含硅部分，衬底的含Si部分顶部的压缩层，以及半导体硅层 在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。

    DUAL STRESSED SOI SUBSTRATES
    8.
    发明申请
    DUAL STRESSED SOI SUBSTRATES 有权
    双应力SOI衬底

    公开(公告)号：US20070202639A1

    公开(公告)日：2007-08-30

    申请号：US11741441

    申请日：2007-04-27

    申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

    发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

    摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

    摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

    MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT
    9.
    发明申请
    MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
    在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流

    公开(公告)号：US20070063277A1

    公开(公告)日：2007-03-22

    申请号：US11162778

    申请日：2005-09-22

    申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

    发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

    IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.

    摘要翻译： 本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极 氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。