公开(公告)号：US10824336B2

公开(公告)日：2020-11-03

申请号：US16360115

申请日：2019-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/06 ,  G06F12/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US20200335170A1

公开(公告)日：2020-10-22

申请号：US16800530

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US20200234781A1

公开(公告)日：2020-07-23

申请号：US16694043

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US10706895B2

公开(公告)日：2020-07-07

申请号：US16406277

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22 ,  G11C16/16 ,  G11C16/08

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US10685721B2

公开(公告)日：2020-06-16

申请号：US16454263

申请日：2019-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

公开(公告)号：US10672477B2

公开(公告)日：2020-06-02

申请号：US16127469

申请日：2018-09-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Han Zhao

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

公开(公告)号：US10580790B2

公开(公告)日：2020-03-03

申请号：US15645635

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L29/74 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  G11C8/10 ,  H01L21/02 ,  H01L27/11529 ,  H01L29/49

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US10580502B2

公开(公告)日：2020-03-03

申请号：US16246009

申请日：2019-01-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US10573728B2

公开(公告)日：2020-02-25

申请号：US16108899

申请日：2018-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: H01L27/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112

Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

公开(公告)号：US10521130B2

公开(公告)日：2019-12-31

申请号：US16197208

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C11/00 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11597

Abstract: Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.