公开(公告)号：US11600631B2

公开(公告)日：2023-03-07

申请号：US16937166

申请日：2020-07-23

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US11462277B2

公开(公告)日：2022-10-04

申请号：US17245275

申请日：2021-04-30

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： G11C16/26 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

摘要： Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US11347401B2

公开(公告)日：2022-05-31

申请号：US17157272

申请日：2021-01-25

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/00 ,  H01L29/51 ,  H01L27/1159 ,  H01L27/11597

摘要： Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

公开(公告)号：US11276437B2

公开(公告)日：2022-03-15

申请号：US16921206

申请日：2020-07-06

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： G11C16/04 ,  G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22 ,  G11C16/16 ,  G11C16/08

摘要： Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US10964400B2

公开(公告)日：2021-03-30

申请号：US16800530

申请日：2020-02-25

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

摘要： Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US10854293B2

公开(公告)日：2020-12-01

申请号：US16868777

申请日：2020-05-07

申请人： MICRON TECHNOLOGY, INC.

发明人： Toru Tanzawa ,  Han Zhao

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

摘要： Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

公开(公告)号：US10770470B2

公开(公告)日：2020-09-08

申请号：US15457473

申请日：2017-03-13

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa ,  Tamotsu Murakoshi ,  Deepak Thimmegowda

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

摘要： Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

公开(公告)号：US10484718B2

公开(公告)日：2019-11-19

申请号：US16197174

申请日：2018-11-20

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： G11C5/06 ,  H04N19/86 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/80 ,  H04N19/82

摘要： Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20190220196A1

公开(公告)日：2019-07-18

申请号：US16360115

申请日：2019-03-21

申请人： MICRON TECHNOLOGY, INC.

发明人： Toru Tanzawa

IPC分类号： G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F12/14

CPC分类号： G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

摘要： Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

公开(公告)号：US20190027194A1

公开(公告)日：2019-01-24

申请号：US16137309

申请日：2018-09-20

申请人： Micron Technology, Inc.

发明人： Toru Tanzawa

IPC分类号： G11C5/06 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/26 ,  G11C16/10 ,  G11C7/12 ,  G11C5/02 ,  G11C7/22 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16

摘要： Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.