公开(公告)号：US11653497B2

公开(公告)日：2023-05-16

申请号：US17498503

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L21/027 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  G11C8/10 ,  H01L21/02 ,  H01L27/11529 ,  H01L29/49

CPC classification number: H01L27/11582 ,  G11C8/10 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/495 ,  H01L29/4966

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US20230015591A1

公开(公告)日：2023-01-19

申请号：US17950556

申请日：2022-09-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L27/112

Abstract: Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

公开(公告)号：US11417671B2

公开(公告)日：2022-08-16

申请号：US17027399

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11575 ,  G11C8/12 ,  G11C16/08

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.

公开(公告)号：US11201165B2

公开(公告)日：2021-12-14

申请号：US16564967

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  G11C5/06 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/80 ,  H04N19/82 ,  H04N19/86

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US10956642B2

公开(公告)日：2021-03-23

申请号：US16432632

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F30/367 ,  G11C7/22 ,  G11C7/10 ,  G11C13/00 ,  G11C29/02

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

公开(公告)号：US20210005624A1

公开(公告)日：2021-01-07

申请号：US17012297

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Tamotsu Murakoshi ,  Deepak Thimmegowda

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

公开(公告)号：US20200303379A1

公开(公告)日：2020-09-24

申请号：US16890673

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11578 ,  H01L21/74 ,  H01L27/02 ,  H01L27/11

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

公开(公告)号：US10784269B2

公开(公告)日：2020-09-22

申请号：US16228574

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11575 ,  G11C8/12

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.

公开(公告)号：US20200007896A1

公开(公告)日：2020-01-02

申请号：US16564967

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H04N19/86 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  G11C16/10 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/80 ,  H04N19/82

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20190267047A1

公开(公告)日：2019-08-29

申请号：US16406277

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  G11C5/02 ,  G11C7/22 ,  H01L27/11551 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/12

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.