公开(公告)号：US20140210021A1

公开(公告)日：2014-07-31

申请号：US13749731

申请日：2013-01-25

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Xia Li ,  Seung H. Kang

IPC: H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/15 ,  G11C11/155 ,  G11C11/161 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same.

Abstract translation: 具有处理区域尺寸的过程中的磁性层在周边形成化学损伤区域。 化学损伤区域的至少一部分被转化为非铁磁性的化学改性的周边部分。 任选地，转化是通过氧化，氮化或氟化，或其组合。

公开(公告)号：US08766384B2

公开(公告)日：2014-07-01

申请号：US13663806

申请日：2012-10-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L29/82

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  G11C2211/5615 ,  H01F10/3254 ,  H01F41/308 ,  H01L27/222 ,  H01L43/08

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract translation: 公开了一种形成磁性隧道结装置的方法，其包括在衬底中形成沟槽，沟槽包括多个侧壁和底壁。 所述方法包括在所述沟槽内靠近所述侧壁之一沉积第一导电材料，并在所述沟槽内沉积第二导电材料。 该方法还包括沉积材料以在沟槽内形成磁隧道结（MTJ）结构。 MTJ结构包括具有固定磁性取向的磁场的固定磁性层，隧道结层和具有可配置磁性取向的磁场的自由磁性层。 该方法还包括选择性地移除MTJ结构的一部分以在MTJ结构中形成开口。

公开(公告)号：US08644063B2

公开(公告)日：2014-02-04

申请号：US13887492

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang

IPC: G11C11/15

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/222 ,  H01L43/08

Abstract: An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs).

Abstract translation: 电子器件制造工艺包括沉积底部电极层。 然后在底部电极层上制造电子器件。 底部电极层的图案化是在制造电子器件之后并且在单独的工艺中对图案化顶部电极进行的。 然后在电子器件上沉积第一电介质层，然后在底部电极层上沉积第一电介质层，然后是顶部电极层。 然后在与底部电极分离的工艺中对顶部电极进行图案化。 单独图案化顶部和底部电极通过减少电子器件之间的电介质材料中的空隙来提高产率。 一种电子设备，其制造工艺非常适用于磁隧道结（MTJ）。

公开(公告)号：US20140011298A1

公开(公告)日：2014-01-09

申请号：US14023899

申请日：2013-09-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L43/12

CPC classification number: H01L21/67011 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/53165

Abstract: A method comprises forming a trench in a substrate. The method also comprises depositing a magnetic tunnel junction (MTJ) structure within the trench. The method further comprises planarizing the MTJ.

Abstract translation: 一种方法包括在衬底中形成沟槽。 该方法还包括在沟槽内沉积磁隧道结（MTJ）结构。 该方法还包括平坦化MTJ。

公开(公告)号：US08614912B2

公开(公告)日：2013-12-24

申请号：US13869086

申请日：2013-04-24

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Xia Li ,  Jung Pill Kim ,  Seung H. Kang

IPC: G11C11/14

CPC classification number: G11C5/025 ,  G11C5/08 ,  G11C11/165 ,  H01L27/0207 ,  Y10T29/49117

Abstract: A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.

Abstract translation: 大规模存储器阵列包括统一大小的虚拟位单元和有源位单元的均匀图案。 大规模存储器阵列中的子阵列由虚拟位单元分隔开。 信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。 类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

公开(公告)号：US20130134533A1

公开(公告)日：2013-05-30

申请号：US13683783

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Xiaochun Zhu ,  Matthew Nowak ,  Xia Li ,  Seung H. Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：US12057394B2

公开(公告)日：2024-08-06

申请号：US17410690

申请日：2021-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Bin Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5226 ,  H01L21/76834 ,  H01L23/53295

Abstract: Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.

公开(公告)号：US11776608B2

公开(公告)日：2023-10-03

申请号：US16672722

申请日：2019-11-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jianguo Yao ,  Bin Yang

IPC: G06N3/063 ,  G11C11/40 ,  G06F9/30 ,  G11C11/54 ,  G11C11/413 ,  H03K19/21

CPC classification number: G11C11/40 ,  G06F9/30029 ,  G06N3/063 ,  G11C11/413 ,  G11C11/54 ,  H03K19/215

Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

公开(公告)号：US11500960B2

公开(公告)日：2022-11-15

申请号：US16666699

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Ye Lu ,  Yandong Gao ,  Xiaochun Zhu ,  Xia Li

IPC: G11C11/419 ,  G06F17/16 ,  G11C11/412 ,  G06N3/063

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

公开(公告)号：US11437781B2

公开(公告)日：2022-09-06

申请号：US16803668

申请日：2020-02-27

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343 ,  H01S5/042 ,  H01S5/34

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.