公开(公告)号：US12084769B2

公开(公告)日：2024-09-10

申请号：US18517387

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Tsun Liu ,  Kuang-Wei Cheng ,  Sheng-chun Yang ,  Chih-Tsung Lee ,  Chyi-Tsong Ni

IPC: C23C16/458 ,  B25B11/00 ,  C23C14/50 ,  H01L21/67 ,  H01L21/683

CPC classification number: C23C16/4586 ,  B25B11/005 ,  C23C14/50 ,  H01L21/67011 ,  H01L21/67017 ,  H01L21/6719 ,  H01L21/6838

Abstract: A chuck vacuum line of a semiconductor processing tool includes a first portion that penetrates a sidewall of a main pumping line of the semiconductor processing tool. The chuck vacuum line includes a second portion that is substantially parallel to the sidewall of the main pumping line and to a direction of flow in the main pumping line. A size of the second portion increases between an inlet end of the second portion and an outlet end of the second portion along the direction of flow in the main pumping line.

公开(公告)号：US12059714B2

公开(公告)日：2024-08-13

申请号：US18492021

申请日：2023-10-23

Applicant: Semes Co., Ltd.

Inventor： Sangmin Lee ,  Joojib Park ,  Euisang Lim

IPC: B08B3/02 ,  B08B7/00 ,  B08B13/00 ,  H01L21/67

CPC classification number: B08B7/0021 ,  B08B13/00 ,  H01L21/67011

Abstract: An apparatus for processing a substrate may include an upper chamber, a lower chamber being combined with the upper chamber and separated from the upper chamber, and at least one driving member for moving the lower chamber in an upward direction and a downward direction. The least one driving member may include a supporting element for supporting the lower chamber, a first driving element for moving the lower chamber and the supporting element, a second driving element for moving the lower chamber, the supporting element and the first driving element, the second driving element being disposed adjacent to the first driving element, and a connecting element for connecting the first driving element to the second driving element. A processing space may be provided between the upper chamber and the lower chamber when the lower chamber is combined with the upper chamber.

公开(公告)号：US20240011189A1

公开(公告)日：2024-01-11

申请号：US18372803

申请日：2023-09-26

Applicant: ASM IP Holding B.V.

Inventor： John Tolle ,  Joseph P. Margetis

IPC: C30B25/14 ,  C30B25/16 ,  C30B25/18 ,  C30B25/08 ,  H01L21/67

CPC classification number: C30B25/14 ,  C30B25/16 ,  C30B25/18 ,  C30B25/08 ,  H01L21/67011

Abstract: Gas-phase reactor systems and methods suitable for use with precursors that are solid phase at room temperature and pressure are disclosed. The systems and methods as described herein can be used to, for example, form amorphous, polycrystalline, or epitaxial layers (e.g., one or more doped semiconductor layers) on a surface of a substrate.

公开(公告)号：US20230253237A1

公开(公告)日：2023-08-10

申请号：US18297787

申请日：2023-04-10

Applicant: SCREEN Holdings Co., Ltd.

Inventor： Scott PRENGLE

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/324

CPC classification number: H01L21/6875 ,  H01L21/67115 ,  H01L21/324 ,  H01L21/67011 ,  H01L21/2686

Abstract: A substrate support device relating to technology disclosed in the description of the present application includes: a holding plate for opposing a substrate bowable by being heated by irradiation with flash light; and a plurality of substrate support pins provided on the holding plate and being for supporting the substrate, wherein the plurality of substrate support pins are arranged at locations where a volume of a space between the holding plate and the substrate in an unbowed state and a volume of a space between the holding plate and the substrate in a bowed state are equal to each other. Breakage of the substrate can be suppressed in a case where the substrate is bowed by flash light.

公开(公告)号：US20230170235A1

公开(公告)日：2023-06-01

申请号：US17989870

申请日：2022-11-18

Applicant: Tokyo Electron Limited

Inventor： Hiromichi FUJII ,  Takashi KUNIEDA

IPC: H01L21/67 ,  G05B19/418

CPC classification number: H01L21/67276 ,  H01L21/67011 ,  G05B19/4183

Abstract: A semiconductor manufacturing apparatus includes: an execution instruction receiving unit that receives an execution instruction for the semiconductor manufacturing apparatus to execute a predetermined process related to an operation control of the semiconductor manufacturing apparatus; an identification information receiving unit that receives an input of identification information of the semiconductor manufacturing apparatus; and an execution unit that executes the predetermined process according to the execution instruction of the predetermined process when identification information of the semiconductor manufacturing apparatus preset in the semiconductor manufacturing apparatus is the same as the identification information of the semiconductor manufacturing apparatus received by the identification information receiving unit.

公开(公告)号：US20190118522A1

公开(公告)日：2019-04-25

申请号：US16220163

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chen Tsao ,  Kuo Liang Lu ,  Ru-Liang Lee ,  Sheng-Hsiang Chuang ,  Yu-Hung Cheng ,  Yeur-Luen Tu ,  Cheng-Kang Hu

IPC: B32B38/10 ,  H01L21/683 ,  H01L21/67 ,  H01L21/68

CPC classification number: B32B38/10 ,  H01L21/67011 ,  H01L21/67092 ,  H01L21/681 ,  H01L21/6835 ,  H01L21/6838

Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates diametrically opposite to each other. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly placed above the pair of bonded substrates and configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.

公开(公告)号：US20180182653A1

公开(公告)日：2018-06-28

申请号：US15654163

申请日：2017-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HyunJin CHONG ,  Myoungseok LEE ,  YuneTech HAN

IPC: H01L21/67 ,  G06F11/36 ,  G06F11/263 ,  H01L21/677 ,  H01L21/66

CPC classification number: H01L21/67242 ,  G05B19/4184 ,  G05B2219/31432 ,  G05B2219/45031 ,  G06F11/263 ,  G06F11/3684 ,  H01L21/67011 ,  H01L21/67276 ,  H01L21/67288 ,  H01L21/67745 ,  H01L22/20

Abstract: An electronic system includes a memory and a processor. The memory stores first setting data of a manufacturing process condition of semiconductor manufacturing equipment. The processor judges whether a change has occurred in the semiconductor manufacturing equipment based on first equipment data from the semiconductor manufacturing equipment and second equipment data stored in the memory before the first equipment data is received. The processor transmits second setting data to the semiconductor manufacturing equipment when the change has occurred in the semiconductor manufacturing equipment and stores the first equipment data in the memory when no change has occurred in the semiconductor manufacturing equipment. The second setting data corresponds to updated first setting data.

公开(公告)号：US09964854B2

公开(公告)日：2018-05-08

申请号：US15472233

申请日：2017-03-28

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Jingfeng Xue ,  Xin Zhang ,  Gui Chen

IPC: H01L21/67 ,  G03F7/20 ,  H01L29/786 ,  H01L21/223 ,  H01L21/265 ,  H01L21/266 ,  H01L27/12 ,  H01L29/66 ,  G02F1/1368 ,  H01L21/027

CPC classification number: G03F7/70058 ,  G02F1/1368 ,  G02F2202/104 ,  H01L21/0274 ,  H01L21/223 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/67011 ,  H01L27/1222 ,  H01L27/127 ,  H01L27/1285 ,  H01L27/1288 ,  H01L29/66492 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78621 ,  H01L29/78675

Abstract: A device for manufacturing an array substrate includes an exposure device for using a halftone mask to form a photoresist pattern layer on a gate insulation layer of a substrate. A polysilicon pattern layer is disposed on the substrate. A gate insulation layer covers the polysilicon pattern layer. The photoresist pattern layer includes a hollow portion corresponding to a heavily doping region of the polysilicon pattern layer, a first photoresist portion corresponding to a lightly doping region of the polysilicon pattern layer, and a second photoresist portion corresponding to an undoped region of the polysilicon pattern layer. The first photoresist portion is thinner than the second photoresist portion. A doping device is used for performing one doping process to the polysilicon pattern layer such that the heavily doping region and the lightly doping region are formed simultaneously.

公开(公告)号：US09923527B2

公开(公告)日：2018-03-20

申请号：US15148668

申请日：2016-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas G. McKay

IPC: H01L27/092 ,  H03F3/193 ,  H01L21/84 ,  H03G1/00 ,  H03F1/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L23/66 ,  H01L27/12 ,  H01L21/67 ,  G06F17/50 ,  H01L21/8238

CPC classification number: H03F3/193 ,  G06F17/5045 ,  H01L21/67011 ,  H01L21/7624 ,  H01L21/823828 ,  H01L21/823892 ,  H01L21/84 ,  H01L23/66 ,  H01L27/0928 ,  H01L27/1203 ,  H01L29/66484 ,  H01L29/7831 ,  H03F1/0205 ,  H03F3/2173 ,  H03F3/3028 ,  H03F2200/267 ,  H03F2200/451 ,  H03F2200/456 ,  H03F2203/30031 ,  H03G1/0005 ,  H03G1/0029

Abstract: At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

公开(公告)号：US20180038009A1

公开(公告)日：2018-02-08

申请号：US15782690

申请日：2017-10-12

Applicant: Lam Research Corporation

Inventor： Daniel Mark Dinneen ,  Steven T. Mayer

IPC: C25D17/16 ,  H01L21/67 ,  C25D21/12 ,  C25D17/00 ,  C25D7/12 ,  H01L21/66 ,  C25D3/38

CPC classification number: C25D17/16 ,  C25D3/38 ,  C25D7/123 ,  C25D17/001 ,  C25D21/12 ,  H01L21/67011 ,  H01L22/12

Abstract: Disclosed herein are methods and apparatuses for electroplating which employ seed layer detection. Such methods and related apparatuses may operate by selecting a wafer for processing, measuring from its surface one or more in-process color signals having one or more color components, calculating one or more metrics, each metric indicative of the difference between one of the in-process color signals and a corresponding set of reference color signals, determining whether an acceptable seed layer is present on the wafer surface based on whether a predetermined number of the one or more metrics are within an associated predetermined range which individually corresponds to that metric, and either electroplating the wafer when an acceptable seed layer is present or otherwise designating the wafer unacceptable for electroplating. The foregoing may then be repeated for one or more additional wafers to electroplate multiple wafers from a set of wafers.