公开(公告)号：US06657267B1

公开(公告)日：2003-12-02

申请号：US10163930

申请日：2002-06-06

Applicant: Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Bin Yu

Inventor： Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/517 ,  H01L21/2652 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a gate and a portion separating the sidewall spacer from a layer of semiconductor material. The liner functions as an etch stop during formation of the sidewall spacer. The liner is removable by an etch process that has substantially no reaction with an isolation region formed in the layer of semiconductor material.

Abstract translation: 公开了半导体器件和制造方法。 半导体器件包括由高K材料构成的衬垫。 衬套具有将侧壁间隔物与栅极分离的部分和将侧壁间隔物与半导体材料层分离的部分。 衬垫在形成侧壁间隔物期间用作蚀刻停止。 衬里可以通过蚀刻工艺去除，该蚀刻工艺基本上不与半导体材料层中形成的隔离区域发生反应。

公开(公告)号：US06642122B1

公开(公告)日：2003-11-04

申请号：US10254850

申请日：2002-09-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract translation: 短通道效应通过形成突变的渐变晕轮廓来控制。 实施例包括顺序形成深源极/漏极区域，离子注入以形成第一深非晶化区域，将杂质离子注入到第一深非晶化区域中以形成第一深光晕植入物，激光热退火以使第一深非晶化区域再结晶并激活深 卤素区域，离子注入以在深晕区域内形成第二浅非晶化区域，离子将杂质注入第二浅非晶区域以形成第二浅光晕植入物和激光热退火以使第二浅无定形区域再结晶并激活浅光晕 地区。 实施例还包括在浅光晕植入物内形成浅源极/漏极延伸部分以及激光热退火以激活浅源极/漏极延伸部分。

公开(公告)号：US06611029B1

公开(公告)日：2003-08-26

申请号：US10290158

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.

Abstract translation: 半导体器件可以包括基板和形成在该副墨滴上的绝缘层。 鳍可以形成在绝缘层上，并且可以包括多个侧表面和顶表面。 第一栅极可以形成在靠近鳍片的多个侧表面中的一个的绝缘层上。 第二栅极，并且可以形成在与第一栅极分离并且靠近鳍片的多个侧表面中的另一个的绝缘层上。

公开(公告)号：US06531368B1

公开(公告)日：2003-03-11

申请号：US09825750

申请日：2001-04-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/268 ,  H01L21/2807 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66583

Abstract: A method of fabricating a semiconductor device, having a locally-formed metal oxide high-k gate insulator, involving: nitriding a substrate to form a thin silicon nitride layer; depositing a thin metal film on the thin silicon nitride layer; forming a localized metal oxide layer from the thin metal film, wherein the a thick nitride layer is deposited on the thin metal film, the thick nitride layer is patterned, the at least one exposed thin metal film portion is locally oxidized, by heating, wherein the oxidizing is performed by local laser irradiation; forming a gate stack having the localized metal oxide layer and a gate electrode, wherein the a thick gate material is deposited in the electrode cavity and on the localized metal oxide layer; the thick gate material is polished, thereby forming the gate electrode; and the thick nitride layer along with the at least one covered thin metal film portion are removed, thereby forming the gate stack; and completing fabrication of the device, and a device thereby formed.

Abstract translation: 一种制造具有局部形成的金属氧化物高k栅极绝缘体的半导体器件的方法，包括：氮化氮化硅层，形成薄的氮化硅层; 在薄氮化硅层上沉积薄金属薄膜; 从所述薄金属膜形成局部金属氧化物层，其中所述厚氮化物层沉积在所述薄金属膜上，所述厚氮化物层被图案化，所述至少一个暴露的金属薄膜部分通过加热而局部氧化，其中 通过局部激光照射进行氧化; 形成具有局部金属氧化物层和栅电极的栅极堆叠，其中厚栅极材料沉积在电极腔和局部金属氧化物层上; 对厚栅极材料进行抛光，从而形成栅电极; 并且去除厚氮化物层与至少一个覆盖的薄金属膜部分，从而形成栅极堆叠; 并完成该装置的制造以及由此形成的装置。

公开(公告)号：US06528858B1

公开(公告)日：2003-03-04

申请号：US10044892

申请日：2002-01-11

Applicant: Bin Yu ,  Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Zoran Krivokapic

Inventor： Bin Yu ,  Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Zoran Krivokapic

IPC: H01L2902

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/76264 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is also disclosed.

Abstract translation: 一种包括NMOS器件和PMOS器件的半导体晶片。 NMOS器件形成为具有高K栅极电介质，并且PMOS器件形成为具有标准K栅极电介质。 还公开了形成NMOS器件和PMOS器件的方法。

公开(公告)号：US06524920B1

公开(公告)日：2003-02-25

申请号：US09779988

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/517 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The gate structure includes L-shaped liners. The semiconductor material can be silicided. A shallow source drain implant can also be provided.

Abstract translation: 集成电路的制造方法利用固相外延形成升高的源极区域和升高的漏极区域。 该方法包括提供非晶半导体材料并使非晶半导体材料结晶而不损坏高k栅介质层。 门结构包括L形衬垫。 半导体材料可以被硅化。 还可以提供浅源极漏极植入物。

公开(公告)号：US06507078B1

公开(公告)日：2003-01-14

申请号：US10131858

申请日：2002-04-25

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

Abstract: A MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon structure disposed on a gate dielectric over the channel region. A drain silicide and a source silicide having a first silicide thickness are formed in the drain region and the source region, respectively. A dielectric layer is deposited over the drain region, the source region, and the gate. The dielectric layer is polished until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. The capping layer on the polysilicon structure of the gate is etched away such that the top of the polysilicon structure is exposed. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon structure are exposed. A polysilicon spacer is formed at the exposed sidewalls at the top portion of the polysilicon structure. A silicidation metal is deposited on the top of the polysilicon structure that is exposed and on the polysilicon spacer. A silicidation anneal is performed with the silicidation metal and the polysilicon structure that is exposed and the polysilicon spacer to form a gate silicide having a second silicide thickness on top of the polysilicon structure of the gate. Because the gate silicide is formed with the added polysilicon spacer at the exposed sidewalls of the polysilicon structure, the gate silicide has a width that is larger than a width of the polysilicon structure of the gate. In addition, the gate silicide is formed in a separate step from the step for forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide.

公开(公告)号：US06492670B1

公开(公告)日：2002-12-10

申请号：US09821258

申请日：2001-03-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2980

CPC classification number: H01L29/66492 ,  H01L29/665

Abstract: A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有局部密封深口袋区域的集成电路的方法利用虚拟或牺牲栅极间隔物。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成袋区域。 在硅化后提供掺杂剂。 开口可以填充间隔件。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06475869B1

公开(公告)日：2002-11-05

申请号：US09793055

申请日：2001-02-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78687

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Abstract translation: 一种制造具有含有锗的沟道区的集成电路的方法。 该方法可以提供双平面栅极结构。 栅极结构可以设置在沟道区域的侧壁上。 含锗的半导体材料可以增加与晶体管相关的电荷迁移率。 外延工艺可以形成通道区域。 可以使用绝缘体上硅。

公开(公告)号：US06465312B1

公开(公告)日：2002-10-15

申请号：US09845602

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665

Abstract: A method of fabricating CMOS transistors having an elevated source-drain structure. The method utilizes the formation of L-shaped spacers on the gate stack followed by amorphous silicon (a-Si) deposition. By way of example, the L-shaped spacers are formed by depositing a first and second spacer layer over the gate stack. The second spacer layer is etched to create a dummy spacer adjacent the gate stack. The regions of the first spacer which are unprotected by the dummy spacer are etched away. The dummy spacer is removed wherein L-shaped spacers of the first spacer layer remain adjacent the gate stack. Deep source-drain implantation is performed on the deposited layer of silicon. After implantation, silicide may be formed on the amorphous silicon at a gate-to-contact spacing determined by the thickness of the L-shaped spacer.

Abstract translation: 一种制造具有升高的源极 - 漏极结构的CMOS晶体管的方法。 该方法利用在栅极堆叠上形成L形间隔物，随后是非晶硅（a-Si）沉积。 作为示例，通过在栅极堆叠上沉积第一和第二间隔层来形成L形间隔物。 蚀刻第二间隔层以产生邻近栅叠层的虚拟间隔物。 被虚拟间隔物保护的第一间隔物的区域被蚀刻掉。 去除虚拟间隔物，其中第一间隔层的L形间隔物保持邻近栅极堆叠。 在硅的沉积层上进行深源极 - 漏极注入。 在注入之后，硅化物可以以由L形间隔物的厚度确定的栅极 - 接触间距在非晶硅上形成。