公开(公告)号：US06818319B2

公开(公告)日：2004-11-16

申请号：US10414282

申请日：2003-04-16

Applicant: I-Chang Tsao ,  Ming-Wei Sun

Inventor： I-Chang Tsao ,  Ming-Wei Sun

IPC: H01L2902

CPC classification number: H01L21/02686 ,  H01L21/2026 ,  H01L21/2205 ,  H01L27/1248 ,  Y10T428/12528 ,  Y10T428/12674 ,  Y10T428/12993 ,  Y10T428/249953 ,  Y10T428/249956 ,  Y10T428/249969 ,  Y10T428/31

Abstract: A diffusion barrier multi-layer structure for a TFT LCD by the LTPS process and the process for fabricating thereof are disclosed. By increasing the coarseness between two layers of the diffusion barrier multi-layer structure with a plasma treatment, or by forming a loose and porous impurity collecting layer between two layers of the diffusion barrier multi-layer structure to trap the impurity atoms, the impurity diffusion can be effectively obstructed.

Abstract translation: 公开了一种通过LTPS工艺制造TFT LCD的扩散阻挡层的多层结构及其制造方法。 通过用等离子体处理来增加扩散阻挡层多层结构的两层之间的粗糙度，或者通过在扩散阻挡层多层结构的两层之间形成松散多孔的杂质收集层来捕获杂质原子，杂质扩散 可以有效阻碍。

公开(公告)号：US06750469B2

公开(公告)日：2004-06-15

申请号：US10233629

申请日：2002-09-04

Applicant: Katsutaro Ichihara ,  Hiroaki Yoda

Inventor： Katsutaro Ichihara ,  Hiroaki Yoda

IPC: H01L2902

CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092 ,  G11C2213/71

Abstract: In a phase-change nonvolatile storage device using a phase-change material as storage cells, which is improved to overcome a basic problem involved in conventional devices of this type and reliably, easily operable as a storage device, the pre-record state of a storage cell is read before recording information in the storage cell, and a write pulse optimum for transition is selected and applied. If the storage cell need not change in phase, the write pulse need not be applied. Alternatively, the pulse is adjusted in waveform of the trailing edge, depending on whether the storage cell should be changed to the amorphous state or the crystal state, to control the crystallization hold time.

Abstract translation: 在使用相变材料作为存储单元的相变型非易失性存储装置中，为了克服与这种类型的常规装置相关的基本问题而能够可靠地容易地作为存储装置操作，改进了相变材料的预记录状态 在将信息记录在存储单元中之前读取存储单元，并且选择并应用用于转换的最佳写入脉冲。 如果存储单元不需要相位改变，则不需要施加写入脉冲。 或者，根据存储单元是否应该改变为非晶态或晶体状态来调整脉冲的后沿波形，以控制结晶保持时间。

公开(公告)号：US06605821B1

公开(公告)日：2003-08-12

申请号：US10142494

申请日：2002-05-10

Applicant: Heon Lee ,  Dennis Lazaroff ,  Neal Meyer ,  Jim Ellenson ,  Ken Kramer ,  Kurt Ulmer ,  David Pursalan ,  Peter Fricke ,  Andrew Koll ,  Andy Van Brockin

Inventor： Heon Lee ,  Dennis Lazaroff ,  Neal Meyer ,  Jim Ellenson ,  Ken Kramer ,  Kurt Ulmer ,  David Pursalan ,  Peter Fricke ,  Andrew Koll ,  Andy Van Brockin

IPC: H01L2902

CPC classification number: H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1675 ,  Y10S438/90

Abstract: The invention includes an electronic memory structure. The electronic memory structure includes a substrate. A substantially planar first conductor is formed adjacent to the substrate. An interconnection layer is formed adjacent to the first conductor. A phase change material element is formed adjacent to the interconnection layer. The interconnection layer includes a conductive interconnect structure extending from the first conductor to the phase change material element. The interconnect structure includes a first surface physically connected to the first conductor. The interconnect structure further includes a second surface attached to the phase change material element. The second surface area of the second surface is substantially smaller than a first surface area of the first surface. A substantially planar second conductor is formed adjacent to the phase change material element.

Abstract translation: 本发明包括电子存储器结构。 电子存储器结构包括基板。 基本上平面的第一导体形成为与基板相邻。 互连层与第一导体相邻地形成。 在互连层附近形成相变材料元件。 互连层包括从第一导体延伸到相变材料元件的导电互连结构。 互连结构包括物理地连接到第一导体的第一表面。 互连结构还包括附接到相变材料元件的第二表面。 第二表面的第二表面积基本上小于第一表面的第一表面积。 形成与相变材料元件相邻的基本平坦的第二导体。

公开(公告)号：US06448593B1

公开(公告)日：2002-09-10

申请号：US09491532

申请日：2000-01-26

Applicant: Masaaki Higashitani ,  Hao Fang

Inventor： Masaaki Higashitani ,  Hao Fang

IPC: H01L2902

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/0266

Abstract: The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.

Abstract translation: 本发明提供一种用于在闪存芯片中提供多晶硅型1型ESD晶体管的方法和装置。 该方法和装置包括提供包括栅极，浮动栅极，中等掺杂结以及源极和漏极的选择栅极晶体管。 所述方法和装置还包括通过执行轻掺杂漏极（LDD）掩模和蚀刻，执行LDD间隔物沉积和LDD间隔物蚀刻以及执行N +注入掩模和N +注入来形成源极和漏极。

公开(公告)号：US06410973B1

公开(公告)日：2002-06-25

申请号：US09339388

申请日：1999-06-24

Applicant: Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L2902

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

公开(公告)号：US06614057B2

公开(公告)日：2003-09-02

申请号：US09778346

申请日：2001-02-07

Applicant: Jeffrey Alan Silvernail ,  Kenneth L. Urbanik

Inventor： Jeffrey Alan Silvernail ,  Kenneth L. Urbanik

IPC: H01L2902

CPC classification number: H01L25/046 ,  H01L31/048 ,  H01L31/049 ,  H01L51/524 ,  H01L51/5256 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: An organic optoelectronic device structure is provided. The structure comprises the following: (a) an organic optoelectronic device selected from an organic light emitting diode, an organic electrochromic display, an organic photovoltaic device and an organic thin film transistor; (b) first and second barrier layers, at least one of the first and second barrier layers permitting transmission of light between the an outer environment and the organic optoelectronic device; (c) a sealing region disposed between the first and second barrier layers, the sealing region cooperating with the first and second barrier layers to enclose the optoelectronic device and restrict transmission of water and oxygen from an outer environment to the optoelectronic device, the sealing region also having at least one associated material that is harmful to the optoelectronic device; and (d) a blocking region disposed between the first and second barrier layers and disposed between the sealing region and the optoelectronic device, the blocking region restricting transmission of the at least one associated material from the sealing region to the optoelectronic device.

公开(公告)号：US06512274B1

公开(公告)日：2003-01-28

申请号：US09603101

申请日：2000-06-22

Applicant: Tsu-Jae King ,  David K. Y. Liu

Inventor： Tsu-Jae King ,  David K. Y. Liu

IPC: H01L2902

CPC classification number: B82Y10/00 ,  G11C5/142 ,  G11C11/39 ,  G11C16/04 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.

Abstract translation: 公开了在其输出特性（作为漏极电压的函数的漏极电流）中呈现负的差分电阻的n沟道金属 - 绝缘体 - 半导体场效应晶体管（MISFET）。 对于固定栅极电压，在晶体管的漏极和源极端子之间流动的MISFET沟道电流首先随着漏极 - 源极电压增加到零伏特而增加。 一旦漏极到源极电压达到预定电平，电流随着漏极 - 源极电压的增加而减小。 在该操作区域中，随着漏极电压的增加，漏极电流降低，器件呈现负的差分电阻。 对应于负差分电阻开始的漏极 - 源极电压也是可调谐的。 此外，漏电流和负差分电阻可以通过调整栅极电压进行电子定制。 所得到的设备可以并入多个有用的应用中，包括作为存储设备的一部分，逻辑设备等。

公开(公告)号：US06501118B2

公开(公告)日：2002-12-31

申请号：US09819988

申请日：2001-03-29

Applicant: Hiroshi Matsubara ,  Syuji Nakao

Inventor： Hiroshi Matsubara ,  Syuji Nakao

IPC: H01L2902

CPC classification number: H01L28/91 ,  H01L27/10814 ,  H01L27/10852

Abstract: A highly reliable semiconductor device having an underlying film with a trench and a conducting material film formed in the trench, a method of manufacturing the same and a method of forming a resist pattern used therein are obtained. The underlying film having an upper surface and the trench is formed. The conducting material film is formed on the upper surface and in the trench. A photo resist film is formed on the conducting material film located on the upper surface of the underlying film and in the trench. The photo resist film is left in the trench whereas the photo resist film is developed and removed outside the trench. The conducting material film located on the upper surface of the underlying film is etched and removed with the photo resist film left in the trench used as a mask.

Abstract translation: 获得了具有在沟槽中形成有沟槽和导电材料膜的底膜的高度可靠的半导体器件，其制造方法和形成其中使用的抗蚀剂图案的方法。 形成具有上表面和沟槽的底层膜。 导电材料膜形成在上表面和沟槽中。 在位于下面的膜的上表面和沟槽中的导电材料膜上形成光刻胶膜。 光致抗蚀剂膜留在沟槽中，而光刻胶膜在沟槽外显影和除去。 蚀刻并除去留在用作掩模的沟槽中的光致抗蚀剂膜的位于下面的膜的上表面上的导电材料膜。

公开(公告)号：US06432521B1

公开(公告)日：2002-08-13

申请号：US09576552

申请日：2000-05-24

Applicant: Shigeru Yagi ,  Seiji Suzuki

Inventor： Shigeru Yagi ,  Seiji Suzuki

IPC: H01L2902

CPC classification number: H01L31/0392 ,  C23C16/303 ,  C30B25/105 ,  C30B29/40 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/2006 ,  H01L29/263 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/0368 ,  H01L31/1852 ,  Y02E10/544 ,  Y10T428/12528 ,  Y10T428/12535 ,  Y10T428/12681 ,  Y10T428/24917

Abstract: This invention provides a Group III-V compound semiconductor that is free from the limitation of the shape and the size, is economical, is excellent in photo-electric characteristics (photo-electric conductivity photo-electromotive current, photo-electromotive force, quantum efficiency), can freely select the optical gap over a broad range, has high performance as a photo-semiconductor, has limited change with time, and is excellent in response, environmental resistance characteristics and high temperature resistance. The Group III-V compound semiconductor contains a Group III element and a Group V element of the Periodic Table as principal components, and contains also 0.1 atom % to 40 atom % of hydrogen atoms and 100 ppm to 20 atom %, based on the sum of the atomic numbers of the Group III element and the Group V element, of at least one element selected from among Be, Mg, Ca, Zn and Sr.

Abstract translation: 本发明提供一种不受形状和尺寸限制的III-V族化合物半导体，其经济性优异的是光电特性（光电导率光电电流，光电动势，量子效率 ），可以在宽范围内自由选择光学间隙，作为光半导体具有高性能，随时间变化有限，响应性，耐环境特性和耐高温性优异。 III-V族化合物半导体含有元素周期表的III族元素和V族元素作为主要成分，并且还包含0.1〜40原子％的氢原子和100〜20原子％ 的III族元素和V族元素的原子序数为选自Be，Mg，Ca，Zn和Sr中的至少一种元素。

公开(公告)号：US06686059B2

公开(公告)日：2004-02-03

申请号：US09960329

申请日：2001-09-24

Applicant: Masayoshi Shirahata

Inventor： Masayoshi Shirahata

IPC: H01L2902

CPC classification number: H01L21/28247 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/6653 ,  Y10T428/12528 ,  Y10T428/1259

Abstract: A semiconductor device having a reduced overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film, tungsten silicide film, and silicon nitride film is partially formed in first and second regions of a silicon substrate, respectively. Sidewall oxide films are formed on side surfaces of the polysilicon films in the first and second regions, respectively. A width of the sidewall of the first structure is smaller than a width of the sidewall of the second structure such that an overlap amount between a second conductive layer and a second impurity region is smaller than an overlap amount between a first conductive layer and a first impurity region.

Abstract translation: 一种在栅电极和延伸部之间具有减小的重叠电容的半导体器件。 具体地，分别在硅衬底的第一和第二区域中形成由多晶硅膜，硅化钨膜和氮化硅膜构成的层叠结构。 侧壁氧化膜分别形成在第一和第二区域中的多晶硅膜的侧表面上。 第一结构的侧壁的宽度小于第二结构的侧壁的宽度，使得第二导电层和第二杂质区域之间的重叠量小于第一导电层和第一导电层之间的重叠量 杂质区。