公开(公告)号：US20240071546A1

公开(公告)日：2024-02-29

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/1201 ,  G11C29/36 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3602

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20240071429A1

公开(公告)日：2024-02-29

申请号：US18233562

申请日：2023-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Nitin CHAWLA ,  Promod KUMAR ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1009 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

公开(公告)号：US20240069096A1

公开(公告)日：2024-02-29

申请号：US18228048

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G01R31/317 ,  G11C11/418 ,  G11C11/419

CPC classification number: G01R31/31724 ,  G11C11/418 ,  G11C11/419

Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.

公开(公告)号：US11901865B2

公开(公告)日：2024-02-13

申请号：US17931863

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Nitin Jain

IPC: H03B5/06 ,  H03B5/36

CPC classification number: H03B5/364 ,  H03B5/06 ,  H03B5/366 ,  H03B2200/0082 ,  H03B2200/0094

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US11900240B2

公开(公告)日：2024-02-13

申请号：US17023144

申请日：2020-09-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Giuseppe Desoli ,  Manuj Ayodhyawasi ,  Thomas Boesch ,  Surinder Pal Singh

IPC: G06N3/06 ,  G06F1/32 ,  G06F9/50 ,  G06F1/08 ,  G06N3/063 ,  G06N3/082 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06N3/063 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/5027 ,  G06N3/082

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：US20240045589A1

公开(公告)日：2024-02-08

申请号：US18488581

申请日：2023-10-17

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Anuj GROVER ,  Thomas BOESCH ,  Surinder Pal SINGH ,  Manuj AYODHYAWASI

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06N3/08

Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.

公开(公告)号：US11885849B2

公开(公告)日：2024-01-30

申请号：US17483014

申请日：2021-09-23

Applicant: Cartesiam

Inventor： He Huang ,  Francois De Grimaudet De Rochebouet

IPC: G01R31/34 ,  G06N20/00 ,  G01R19/165

CPC classification number: G01R31/343 ,  G01R19/165 ,  G06N20/00

Abstract: A method can be used for supervising the operation of a machine powered with electric current. The method includes operating the machine in a normal operation mode, repeatedly performing a learning phase for learning the normal operation machine of the machine to create a knowledge base, autonomously switching from the learning phase into a supervision phase when the knowledge base is considered to have been created, and repeatedly performing the supervision phase.

公开(公告)号：US20240005956A1

公开(公告)日：2024-01-04

申请号：US18448737

申请日：2023-08-11

Applicant: STMicroelectronics International N.V.

Inventor： Paolo Pulici ,  Michele Bartolini ,  Enrico Sentieri ,  Enrico Mammei ,  Matteo Tonelli ,  Dennis Hogg

IPC: G11B5/60

CPC classification number: G11B5/607 ,  G11B5/6017

Abstract: A system for determining a fly height includes a first head of a disk drive, a second head of the disk drive, a capacitive sensor circuit coupled to the first head and the second head, and a logic device coupled to the capacitive sensor circuit. The capacitive sensor circuit is configured to measure a first capacitance between the first head and the first disk, remove noise from the first capacitance using a second capacitance between the second head and the second disk, and based thereon determine a corrected first capacitance. The logic device is configured to determine the fly height between the first head and the first disk using the corrected first capacitance.

公开(公告)号：US11863066B2

公开(公告)日：2024-01-02

申请号：US18168936

申请日：2023-02-14

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07 ,  G11C5/14

CPC classification number: H02M3/07 ,  G11C5/145 ,  H02M3/071

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US11860993B2

公开(公告)日：2024-01-02

申请号：US17396137

申请日：2021-08-06

Applicant: STMicroelectronics International N.V.

Inventor： Dhulipalla Phaneendra Kumar

IPC: G06F21/45 ,  G06F21/31

CPC classification number: G06F21/45 ,  G06F21/31

Abstract: A method of operating an electronic device includes generating scramble control codes. The scramble codes are generated by generating a random number, shifting the random number to produce a shifted random number, generating control signals by selecting different subsets of the shifted random number, and generating scramble control words by selecting different subsets of the random number based upon the control signals. The method further includes receiving a password comprised of sub-words and scrambling those sub-words according to the scramble control codes, retrieving a verification word comprised of sub-words and scrambling those sub-words according to the scramble control codes, and comparing the scrambled sub-words of the password to the scrambled sub-words of the verification word to thereby authenticate an external device that provided the password.