公开(公告)号：US20020005733A1

公开(公告)日：2002-01-17

申请号：US09949703

申请日：2001-09-10

Applicant: STMicroelectronics Limited

Inventor： William B. Barnes

IPC: H03K017/16

CPC classification number: H01L29/0634 ,  H03K3/356113 ,  H03K17/102

Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage. This has the effect that the first switch is effectively isolated from the third switch during switching and allows a time delay during which the first switch is switched off under control of the control circuit and the second switch switches on. The provision of the voltage dependent second switch eliminates any nullcurrent battlesnull occurring between the first and third switch during switching.

Abstract translation: 讨论了与已知类型的开关电路相比具有改进的开关时间的开关电路。 电路包括串联连接的三个开关，第一开关连接到上电源，第三开关连接到较低电源。 电路的输出连接到位于第二和第三开关之间的连接处的电路节点。 开关电路的输入也连接到第三开关，并且还连接到控制电路，该控制电路提供另外的输出以控制第一开关。 第二开关响应于电路节点处的电压，使得第二开关仅在输出节点处的电压下降到低于上电源电压时才导通。 这具有在开关期间第一开关与第三开关有效隔离的作用，并且允许第一开关在控制电路的控制下被切断并且第二开关导通的时间延迟。 提供依赖于电压的第二开关消除了在切换期间在第一和第三开关之间发生的任何“当前的战斗”。

公开(公告)号：US06133796A

公开(公告)日：2000-10-17

申请号：US221296

申请日：1998-12-23

Applicant: Trevor Monk

Inventor： Trevor Monk

IPC: H03K23/54 ,  H03K23/66 ,  H03L7/16

CPC classification number: H03L7/183 ,  H03K23/544 ,  H03K23/66 ,  H03K23/667

Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages. The circuit includes a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and wherein the second plurality M of transistor stages includes at least some of said first plurality N of transistor stages, including said first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages. The circuit includes a switching circuit having at least two inputs and arranged to selectively connect to the first stage, the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Abstract translation: 可编程分频电路包括以N分频序列连接的第一多个N个相似的晶体管级，其中N为奇整数，晶体管级配置成使得当最后级的输出提供给第一级时 按照该顺序，分频电路作为N分频电路工作，其中产生一个输出信号，对于施加到晶体管级的时钟信号的每N个周期，产生一个周期。 该电路包括可选择地以M分频序列与第二多个晶体管级M连接的三态反相器，其中M为偶数整数，并且其中第二多个M晶体管级包括至少部分所述第一 多个N个晶体管级，包括所述第一级，由此当M分频序列中的最后级的输出被提供给第一级时，该电路作为除M电路工作，其中输出信号 被产生，其对于施加到晶体管级的时钟信号的每M个周期具有一个周期。 该电路包括具有至少两个输入并且被布置为选择性地连接到第一级的输入，N分频或M分频序列中的最后级的输出，由此该电路可以是 被编程为以N分频或M分频电路运行。

公开(公告)号：US6052806A

公开(公告)日：2000-04-18

申请号：US519192

申请日：1995-08-25

Applicant: Robert Beat

Inventor： Robert Beat

IPC: G01R31/28 ,  G06F11/27 ,  G11C17/00 ,  G11C29/00 ,  G11C29/12

CPC classification number: G06F11/27

Abstract: An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for carrying out at least one function in respect of the operational circuitry. Input means are provided to permit the input of command data in a normal mode of operation and to permit the input of test data in a test mode of operation. Control circuitry has an input to receive command data from the input means. The control circuitry is arranged to generate, in response to the command data, control signals to control at least one of the peripheral circuits in the normal mode of operation. A control bus is connected between the control circuitry and the peripheral circuits and is arranged to carry control signals from the control circuitry to at least one peripheral circuit. Test circuitry is also provided which has an input arranged to receive test data from the input means. The test circuitry also has an output connected to the control bus and is arranged such that in the test mode of operation, the test data is supplied to at least one peripheral circuit from the test circuitry via the control bus.

Abstract translation: 集成电路装置包括例如用于执行集成电路装置的操作的存储器形式的操作电路。 此外，至少一个外围电路连接到操作电路，用于执行关于操作电路的至少一个功能。 提供输入装置以允许在正常操作模式下输入命令数据，并允许在测试操作模式下输入测试数据。 控制电路具有从输入装置接收命令数据的输入。 控制电路被布置成响应于命令数据产生控制信号，以控制正常操作模式中的至少一个外围电路。 控制总线连接在控制电路和外围电路之间，并被布置成将控制信号从控制电路传送到至少一个外围电路。 还提供测试电路，其具有布置成从输入装置接收测试数据的输入。 测试电路还具有连接到控制总线的输出，并且被布置为使得在测试操作模式下，测试数据经由控制总线从测试电路提供给至少一个外围电路。

公开(公告)号：US08151151B2

公开(公告)日：2012-04-03

申请号：US12657228

申请日：2010-01-15

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/02 ,  G11C29/00

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US07836300B2

公开(公告)日：2010-11-16

申请号：US10705782

申请日：2003-11-10

Applicant: Andrew Dellow ,  Rodrigo Cordero

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: H04L29/06 ,  H04L9/00 ,  H04L9/08 ,  H04N7/167

CPC classification number: H04N21/42623 ,  H04N21/26613 ,  H04N21/4623

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with the television signals include control words and common keys. The common keys are received in encrypted form, encrypted according to a secret key unique to each semiconductor integrated circuit. The input interface is connected to a decryption circuit whereby the only manner of providing the common keys to the circuit are in encrypted form encrypted according to the secret key. Due to the monolithic nature of the circuit, no secrets are exposed and the system is secure.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，该电路包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 用电视信号广播的控制信号包括控制字和公共密钥。 公共密钥以加密形式接收，根据每个半导体集成电路独有的秘密密钥进行加密。 输入接口连接到解密电路，由此向电路提供公共密钥的唯一方式是根据密钥加密的加密形式。 由于电路的整体性质，没有暴露的秘密和系统是安全的。

公开(公告)号：US07797438B2

公开(公告)日：2010-09-14

申请号：US10380994

申请日：2001-09-19

Applicant: Steven Haydock

Inventor： Steven Haydock

IPC: G06F15/16

CPC classification number: H04N21/434

Abstract: Data reception apparatus for receiving and processing a data stream including a stream of data units, the data apparatus comprising: a buffer; a data reception controller for receiving data units from the data stream, storing received data units in the buffer, and if the amount of data from the data stream that is stored in the buffer exceeds a predetermined amount, generating a buffer load interrupt for the data stream; and a processor responsive to the buffer load interrupt to: a) disable handling of further buffer load interrupts for the data stream; and b) repeatedly activate a routine to process a single data unit from the data stream that is stored in the buffer until all the data units in the buffer have been processed and then reset the buffer.

Abstract translation: 一种用于接收和处理包括数据单元流的数据流的数据接收装置，所述数据装置包括：缓冲器; 数据接收控制器，用于从数据流接收数据单元，将接收到的数据单元存储在缓冲器中，并且如果来自存储在缓冲器中的数据流的数据量超过预定量，则为数据生成缓冲器加载中断 流; 以及响应于所述缓冲器加载中断的处理器，以：a）禁止处理所述数据流的进一步的缓冲器加载中断; 并且b）重复激活例程以从存储在缓冲器中的数据流处理单个数据单元，直到缓冲器中的所有数据单元已被处理，然后重置缓冲器。

公开(公告)号：US07702974B2

公开(公告)日：2010-04-20

申请号：US11015772

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/26

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US07698718B2

公开(公告)日：2010-04-13

申请号：US11461306

申请日：2006-07-31

Applicant: Andrew Dellow ,  Peter Bennett

Inventor： Andrew Dellow ,  Peter Bennett

IPC: H04N7/16 ,  H04N7/167

CPC classification number: H04N7/1675 ,  H04L9/0891 ,  H04L9/3247 ,  H04L2209/56 ,  H04L2209/601 ,  H04N21/4181 ,  H04N21/43607 ,  H04N21/4405 ,  H04N21/8166

Abstract: An integrated circuit restricts use of a data item and includes a data memory storing the data item; a value memory storing a value; a signature input that receives a signature derived from data in a data item field and a value in a value field, the signature being in a coded form; a decoding circuit that decodes the signature and outputs information representing the data in the data item field and the value in the value field; and a comparison circuit that receives the decoding circuit output, determines whether the information representing the data from the data item field corresponds to the stored data item and whether the information representing the value from the value field corresponds to the value stored in the value memory, and outputs a comparison signal according to the determinations. The circuit restricts the use of the data item according to the comparison signal.

Abstract translation: 集成电路限制数据项的使用，并且包括存储数据项的数据存储器; 存储值的值存储器; 签名输入，其接收从数据项字段中的数据和值字段中的值导出的签名，所述签名处于编码形式; 解码电路，对所述签名进行解码并输出表示所述数据项字段中的数据的信息和所述值字段中的值; 以及接收解码电路输出的比较电路，确定表示来自数据项字段的数据的信息是否对应于所存储的数据项，以及表示来自值字段的值的信息是否对应于存储在值存储器中的值， 并根据确定输出比较信号。 电路根据比较信号限制数据项的使用。

公开(公告)号：US07506810B2

公开(公告)日：2009-03-24

申请号：US11152673

申请日：2005-06-14

Applicant: Jeremy Whaley ,  Matthew Hutson

Inventor： Jeremy Whaley ,  Matthew Hutson

IPC: G06K7/06

CPC classification number: G06K7/0069 ,  G06K7/0021

Abstract: A card reader reads data stored on a card. A contact signal is produced whose state is indicative of the presence or absence of electrical contact between the card and the card reader. A high state indicates the presence of electrical contact and a low state indicates the absence of electrical contact. Upon insertion of the card into the card reader, vibrations and other mechanical perturbations of the card cause the state of the contact signal to fluctuate rapidly between high and low states. The state of the contact signal is periodically sampled for a predetermined period of time and the number of samples for which the contact signal was high are counted. If the number of high samples exceeds a threshold then stable electrical contact is deemed to have been established between the card and the card reader and a system reset is performed.

Abstract translation: 读卡器读取存储在卡上的数据。 产生接触信号，其状态指示卡和读卡器之间是否存在电接触。 高电平表示存在电接触，低电位表示不存在电接触。 在将卡插入读卡器时，卡的振动和其他机械扰动导致接触信号的状态在高状态和低状态之间迅速波动。 接触信号的状态在预定的时间周期内被周期性地采样，并对接触信号为高的样本数进行计数。 如果高样本数超过阈值，则认为在卡和读卡器之间建立稳定的电接触，并执行系统复位。

公开(公告)号：US07496656B2

公开(公告)日：2009-02-24

申请号：US10380923

申请日：2001-09-19

Applicant: Steven Haydock

Inventor： Steven Haydock

IPC: G06F15/16 ,  G06F15/173 ,  G06F9/00 ,  G06F9/30 ,  G06F11/00

CPC classification number: H04N21/434 ,  G06F9/30072 ,  G06F9/3853

Abstract: A method for processing an instruction word in a data processing system, the instruction word comprising a plurality of instruction bit positions, each bit position corresponding to an instruction actions, and a status of the bit at an instruction bit position indicating whether the instruction action corresponding to that bit position should be performed; the method comprising: forming a plurality of single action words, each single action word corresponding to one of the instruction actions and having a bit set at the bit position corresponding to that instruction actions and all its other bits un-set; forming a common action word having bits set at the bit positions corresponding to the instruction actions of any of the single action words and all its other bits un-set; comparing the instruction word and the common action word, and if the instruction word and the common action word have no bits set in common terminating processing of the instruction, and otherwise: repeating for successive single action words the steps of: comparing the instruction word and the respective single action word, and if the instruction word and the respective single action word have a bit set in common, performing the action corresponding to that single action word, and setting the instruction word to be equal to the present value of the instruction word exclusive-Ored with the respective single action word; until all the bits in the instruction word are zero.

Abstract translation: 一种用于在数据处理系统中处理指令字的方法，所述指令字包括多个指令位位置，与指令动作相对应的每个位位置，以及指令位位置处的位的状态，指示是否对应指令动作 应该执行该位位置; 所述方法包括：形成多个单动作词，每个单个动作词对应于所述指令动作中的一个，并且在与所述指令动作相对应的位位置处设置位，并且其所有其他位未设置; 形成具有在与单个动作字中的任一个的指令动作相对应的位位置位和未设置的所有其他位的位设置的公共动作字; 比较指令字和公共动作字，并且如果指令字和公共动作字在指令的公共终止处理中没有设置位，否则：对于连续的单个动作字重复以下步骤：将指令字和 相应的单个动作字，并且如果指令字和相应的单个动作字具有被设置为共同的位，则执行与该单个动作字对应的动作，并且将指令字设置为等于指令字的当前值 独家使用单一动作单词; 直到指令字中的所有位都为零。