公开(公告)号：US20140340422A1

公开(公告)日：2014-11-20

申请号：US13896105

申请日：2013-05-16

Applicant: Analog Devices Technology

Inventor： Himanshu Srivastava

IPC: G06T11/60

Abstract: An apparatus includes a processing unit that divides an overlay buffer into a plurality of macro blocks, draws a graphic primitive object including a plurality of pixels, identifies one of the plurality of macro blocks upon a determination that the plurality of pixels has crossed a boundary of the one of the plurality of macro blocks, and image processes the one of the plurality of macro blocks.

Abstract translation: 一种装置包括：处理单元，其将覆盖缓冲区划分成多个宏块，绘制包括多个像素的图形原始对象，在确定所述多个像素已经跨越所述多个像素的边界时识别所述多​​个宏块中的一个， 多个宏块中的一个，并且图像处理多个宏块中的一个。

公开(公告)号：US20140340150A1

公开(公告)日：2014-11-20

申请号：US14185701

申请日：2014-02-20

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Dennis A. Dempsey ,  Sean Brennan ,  Colin Lyden ,  John Jude O'Donnell

IPC: H03F3/45

CPC classification number: H03F1/223 ,  H03F3/45475 ,  H03F2200/156 ,  H03F2203/45116 ,  H03F2203/45528 ,  H03F2203/45536 ,  H03F2203/45696 ,  H03M1/765 ,  H03M1/808

Abstract: An example transconductance circuit is provided in accordance with one embodiment. The transconductance circuit can comprise: an output node; at least one transistor; a variable resistance; and a differential amplifier; wherein the at least one transistor and the variable resistance are in series connection with the output node, an output of the differential amplifier is connected to a control node of the at least one transistor, a first input of the amplifier is responsive to an input signal, and a second input of the amplifier is responsive to a voltage across the variable resistance. Such a circuit may overcome noise problems in transconductance circuits which operate over a wide range of input signals with a fixed resistor in series with the at least one transistor.

Abstract translation: 根据一个实施例提供了示例性跨导电路。 跨导电路可以包括：输出节点; 至少一个晶体管; 可变电阻; 和差分放大器; 其中所述至少一个晶体管和所述可变电阻与所述输出节点串联连接，所述差分放大器的输出端连接到所述至少一个晶体管的控制节点，所述放大器的第一输入端响应于输入信号 并且放大器的第二输入响应可变电阻两端的电压。 这种电路可以克服在具有与至少一个晶体管串联的固定电阻器的宽范围的输入信号上工作的跨导电路中的噪声问题。

公开(公告)号：US08878712B2

公开(公告)日：2014-11-04

申请号：US13829257

申请日：2013-03-14

Applicant: John Cullinane ,  Frederick Carnegie Thompson

Inventor： John Cullinane ,  Frederick Carnegie Thompson

IPC: H03M1/36 ,  H03M1/34

CPC classification number: H03M1/0673 ,  H03M1/145 ,  H03M1/365

Abstract: A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.

Abstract translation: 闪存ADC电路可以包括提供参考信号的参考梯形图和多个比较器，每个比较器基于一对输入信号与一对参考信号的比较来提供输出。 至少一对比较器可以在每个比较器处以不同的参考信号取向接收相同的一对参考信号。 闪存ADC可以包括用于在一对比较器之间交换一对参考信号的开关网络。

公开(公告)号：US20140270018A1

公开(公告)日：2014-09-18

申请号：US13844759

申请日：2013-03-15

Applicant: Analog devices Technology

Inventor： Haim Primo ,  Yosef Stein

IPC: H04L25/03

CPC classification number: H04L25/03006 ,  H03D3/009 ,  H03D7/165 ,  H03D2200/0054 ,  H04B1/30 ,  H04L27/3863

Abstract: An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.

Abstract translation: 电路包括配置成产生第一参考信号的本地振荡器和具有与第一参考信号相关的预定相移的第二参考信号，配置为将第一参考信号注入到输入信号并产生第一参考信号的I信道混合器 输出，配置为将第一输出与常数因子相乘以产生第二输出的补偿混合器，被配置为近似地衰减第二输出中的频率以产生第三输出的第一低通滤波器，以及第一校正滤波器， 第三输出产生第四输出。 第一校正滤波器被配置为减少第一低通滤波器和第二低通滤波器之间的信道脉冲响应失配，其被配置为衰减输入信号的Q信道中的频率。 在具体实施例中，相移包括45°。

公开(公告)号：US20140268936A1

公开(公告)日：2014-09-18

申请号：US14051702

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yanfeng Lu ,  Bin Shao

IPC: H02M1/36

CPC classification number: H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K2217/0081

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

Abstract translation: 至少一个实施例提供了一种纳米功率升压调节器从能量收集应用的超低电压（例如0.3V〜0.5V）启动的方法。 该方法不一定需要特殊的过程或任何外部组件，例如机械开关。 启动电路可以包括异步升压电路，用于堆叠功率NMOS晶体管，环形振荡器和/或电荷泵以及相关电路对输出进行充电。

公开(公告)号：US20140266821A1

公开(公告)日：2014-09-18

申请号：US13869454

申请日：2013-04-24

Applicant: Hajime SHIBATA

Inventor： Hajime SHIBATA

IPC: H03M1/00

CPC classification number: H03M1/44 ,  H03M1/001 ,  H03M1/002 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/167

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。

公开(公告)号：US20140266314A1

公开(公告)日：2014-09-18

申请号：US14204851

申请日：2014-03-11

Applicant: Analog Devices Technology

Inventor： Santiago Iriarte ,  John A. Cleary

IPC: H03K5/24

CPC classification number: H03K5/2472

Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.

Abstract translation: 一种电源监视电路，用于监视与参考节点相比的电源节点处的电压，所述电源监视电路包括第一场效应晶体管和第一和第二降压组件，所述第一和第二降压组件以电流节点和 参考节点，并且每个具有第一和第二节点，并且其中第一降压部件的第一节点连接到场效应晶体管的第一和第二节点中的一个，并且场效应晶体管的栅极连接到第二节点 第一降压部件的节点，并且从与第一场效应晶体管制成的连接取得输出信号。

公开(公告)号：US20140266306A1

公开(公告)日：2014-09-18

申请号：US13797038

申请日：2013-03-12

Applicant: John CULLINANE

Inventor： John CULLINANE

IPC: H03K3/36

CPC classification number: H03K3/012 ,  H03K3/356139

Abstract: Embodiments of the present disclosure may provide a dynamic latch circuit with increased speed and that can perform comparisons on low input signals. The dynamic latch circuit may include a first input transistor receiving a first input signal and a second input transistor receiving a second input signal. A cross coupled inverters may be included to provide a first and second output signals based on the sampled input signals from the first and second input transistors. A reset circuit may be included to reset the first and second outputs to a reference voltage. The latch circuit may include an impedance controller coupled in parallel with the first and second input transistors.

Abstract translation: 本公开的实施例可以提供具有增加的速度的动态锁存电路，并且可以对低输入信号执行比较。 动态锁存电路可以包括接收第一输入信号的第一输入晶体管和接收第二输入信号的第二输入晶体管。 可以包括交叉耦合的反相器以基于来自第一和第二输入晶体管的采样的输入信号来提供第一和第二输出信号。 可以包括复位电路以将第一和第二输出复位到参考电压。 锁存电路可以包括与第一和第二输入晶体管并联耦合的阻抗控制器。

公开(公告)号：US20140257821A1

公开(公告)日：2014-09-11

申请号：US13788062

申请日：2013-03-07

Applicant: Robert Adams ,  Maikael Mortensen

Inventor： Robert Adams ,  Maikael Mortensen

IPC: G10L21/06

CPC classification number: G10L21/06 ,  G06F1/3206 ,  G10L15/28 ,  G10L25/48 ,  G10L25/78 ,  G10L25/84 ,  G10L25/87 ,  G10L25/93 ,  G10L2015/088 ,  G10L2025/783 ,  G10L2025/786

Abstract: A system for processor wake-up based on sensor data includes an audio buffer, an envelope buffer, and a processor. The audio buffer is configured to store a first data from a sensor. The first data is generated according to a first sampling rate. The envelope buffer is configured to store a second data, which is derived from the first data according to a second sampling rate, which is less than the first sampling rate. The processor is configured to wake up periodically from an idle state and read the second data from the envelope buffer. If the second data indicates an activity, the processor is configured to read the first data from the audio buffer. If the second data does not indicate an activity, the processor is configured to return to the idle state.

Abstract translation: 基于传感器数据的用于处理器唤醒的系统包括音频缓冲器，包络缓冲器和处理器。 音频缓冲器被配置为存储来自传感器的第一数据。 根据第一采样率产生第一数据。 包络缓冲器被配置为存储第二数据，其根据小于第一采样率的第二采样率从第一数据导出。 处理器被配置为周期性地从空闲状态唤醒并从包络缓冲器读取第二数据。 如果第二数据指示活动，则处理器被配置为从音频缓冲器读取第一数据。 如果第二个数据不表示活动，则处理器被配置为返回到空闲状态。

公开(公告)号：US20140253237A1

公开(公告)日：2014-09-11

申请号：US13787065

申请日：2013-03-06

Applicant: Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

Inventor： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  H03F3/45183 ,  H03M1/164

Abstract: An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage non-inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.

Abstract translation: 一种放大器，包括：输入节点; 输出节点; 具有增益级反相输入，增益级非反相输入和增益级输出的增益级; 连接在增益级输出和增益级反相输入之间的信号路径中的反馈电容器; 连接在输入节点和增益级非反相输入端之间的采样电容器和与反馈电容器并联的可控阻抗，其中可控阻抗可操作以在其不影响电流流过的第一阻抗状态 反馈电容器和与反馈电容器配合的第二阻抗状态形成带宽限制电路。