公开(公告)号：US09231539B2

公开(公告)日：2016-01-05

申请号：US13787065

申请日：2013-03-06

申请人： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

发明人： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

IPC分类号： H03F3/45 ,  H03M1/16

CPC分类号： H03F3/45076 ,  H03F3/45183 ,  H03M1/164

摘要： An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.

摘要翻译： 一种放大器，包括：输入节点; 输出节点; 具有增益级反相输入，增益级非反相输入和增益级输出的增益级; 连接在增益级输出和增益级反相输入之间的信号路径中的反馈电容器; 连接在所述输入节点和所述增益级反相输入端之间的采样电容器，以及与所述反馈电容器并联的可控阻抗，其中所述可控阻抗可操作以在其不影响通过所述反馈的电流的第一阻抗状态之间切换 电容器和与反馈电容器配合的第二阻抗状态形成带宽限制电路。

公开(公告)号：US20140253237A1

公开(公告)日：2014-09-11

申请号：US13787065

申请日：2013-03-06

申请人： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

发明人： Colin G. Lyden ,  Christopher Peter Hurrell ,  Derek Hummerston

IPC分类号： H03F3/45

CPC分类号： H03F3/45076 ,  H03F3/45183 ,  H03M1/164

摘要： An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage non-inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.

摘要翻译： 一种放大器，包括：输入节点; 输出节点; 具有增益级反相输入，增益级非反相输入和增益级输出的增益级; 连接在增益级输出和增益级反相输入之间的信号路径中的反馈电容器; 连接在输入节点和增益级非反相输入端之间的采样电容器和与反馈电容器并联的可控阻抗，其中可控阻抗可操作以在其不影响电流流过的第一阻抗状态 反馈电容器和与反馈电容器配合的第二阻抗状态形成带宽限制电路。

公开(公告)号：US08040264B2

公开(公告)日：2011-10-18

申请号：US12717448

申请日：2010-03-04

申请人： Derek Hummerston ,  Christopher Peter Hurrell ,  Colin Lyden

发明人： Derek Hummerston ,  Christopher Peter Hurrell ,  Colin Lyden

IPC分类号： H03M1/06

CPC分类号： H03M1/12

摘要： A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

摘要翻译： 一种管线模数转换器，包括：第一模数转换器，用于确定模数转换结果的第一部分，以及用于形成残留信号; 用于放大残留信号的放大器，所述放大器包括用于对放大器的偏移进行采样的至少一个偏移采样电容器，其中至少一个电阻与所述至少一个电容器相关联以形成滤波器，并且所述至少一个 电阻器是可变的，使得在偏移的采样期间，可以在第一带宽和小于第一带宽的第二带宽之间切换放大器带宽。

公开(公告)号：US07181635B2

公开(公告)日：2007-02-20

申请号：US10723464

申请日：2003-11-26

申请人： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

发明人： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC分类号： G06F1/26

CPC分类号： H03M1/004 ,  G06F1/3209 ,  H03M1/002 ,  H03M1/46 ,  H03M1/462 ,  H03M1/70 ,  H04W52/0287 ,  Y02D70/122

摘要： A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

摘要翻译： 一种用于将设备放置在所选择的操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，在第二逻辑状态中断言设备选择信号，并在第一用户控制的时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。 所选择的操作模式可以是诸如菊花链操作模式的降低的功耗模式，例如或设备的另一操作模式，或者是适应模拟输入范围的编程的模式。

公开(公告)号：US20050035895A1

公开(公告)日：2005-02-17

申请号：US10723464

申请日：2003-11-26

申请人： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

发明人： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC分类号： G06F1/32 ,  H03M1/00 ,  H03M1/12 ,  H03M1/42 ,  H03M1/46 ,  H03M1/70 ,  H04M1/73 ,  H03M1/34

CPC分类号： H03M1/004 ,  G06F1/3209 ,  H03M1/002 ,  H03M1/46 ,  H03M1/462 ,  H03M1/70 ,  H04W52/0287 ,  Y02D70/122

摘要： A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

摘要翻译： 一种用于将设备放置在所选择的操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，在第二逻辑状态中断言设备选择信号，并在第一用户控制的时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。 所选择的操作模式可以是诸如菊花链操作模式的降低的功耗模式，例如或设备的另一操作模式，或者是适应模拟输入范围的编程的模式。

公开(公告)号：US06681332B1

公开(公告)日：2004-01-20

申请号：US09523610

申请日：2000-03-13

申请人： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

发明人： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC分类号： G06F132

CPC分类号： G06F1/3209 ,  H03M1/002

摘要： A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

摘要翻译： 一种用于将设备放置在降低的功耗操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，以第二逻辑状态断言设备选择信号，并在第一预定时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。