公开(公告)号：US09755602B2

公开(公告)日：2017-09-05

申请号：US14258634

申请日：2014-04-22

Applicant: Analog Devices Technology ,  Analog Devices, Inc.

Inventor： Eberhard Brunner ,  Jeff Venuti

IPC: H04B1/04 ,  H03G3/30 ,  H03F3/19 ,  H03F3/45 ,  H03G1/00 ,  H03C1/62

CPC classification number: H03G3/3042 ,  H03F3/19 ,  H03F3/4508 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45116 ,  H03F2203/45154 ,  H03F2203/45306 ,  H03G1/0023

Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.

公开(公告)号：US09460354B2

公开(公告)日：2016-10-04

申请号：US13888993

申请日：2013-05-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Joseph Fernandez ,  Sreenath Kottekkode

IPC: G06K9/00 ,  G06K9/46 ,  G06K9/66 ,  G06K9/62 ,  H04N7/18

CPC classification number: G06K9/00805 ,  G06K9/00791 ,  G06K9/4642 ,  G06K9/6269

Abstract: Objects are detected in real-time at full VGA 30 frame per second resolution. A preprocessor performs run-length encoding (RLE) and generates a summed area table (SAT) of an image. The RLE and SAT are used to identify candidate objects and to iteratively refine their boundaries. A histogram of gradients (HoG) and support vector machine (SVM) then reliably classify the object. The method may be part of an advanced driver assistance system (ADAS).

Abstract translation: 实时检测物体的全VGA每秒30帧分辨率。 预处理器执行游程长度编码（RLE）并生成图像的求和区域表（SAT）。 RLE和SAT用于识别候选对象并迭代地改进边界。 梯度（HoG）和支持向量机（SVM）的直方图然后可靠地对对象进行分类。 该方法可以是高级驾驶员辅助系统（ADAS）的一部分。

公开(公告)号：US09350308B2

公开(公告)日：2016-05-24

申请号：US14296247

申请日：2014-06-04

Applicant: Analog Devices Technology

Inventor： Eberhard Brunner

IPC: H03F3/45 ,  H03G1/00 ,  H03F3/04

CPC classification number: H03G1/0017 ,  H03F3/04 ,  H03F3/45 ,  H03F3/45085 ,  H03F2203/45274 ,  H03F2203/45392 ,  H03F2203/45601 ,  H03F2203/45612 ,  H03G1/0023

Abstract: A transconductance gain stage including a pair of gain transistors, each gain transistor having a base and an emitter, the emitter of each gain transistor electrically coupled to a degenerating resistor, and the emitter of each gain transistor connected to a gain resistor.

Abstract translation: 跨导增益级包括一对增益晶体管，每个增益晶体管具有基极和发射极，每个增益晶体管的发射极电耦合到退化电阻器，并且每个增益晶体管的发射极连接到增益电阻器。

公开(公告)号：US09292763B2

公开(公告)日：2016-03-22

申请号：US13951193

申请日：2013-07-25

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bijesh Poyil ,  Ramandeep Singh Kukreja ,  Anil M. Sripadarao

IPC: G06K9/46 ,  G06K9/48 ,  G06T7/00

CPC classification number: G06K9/48 ,  G06K9/4638 ,  G06T7/11 ,  G06T7/12 ,  G06T7/13 ,  G06T7/136 ,  G06T7/181 ,  G06T7/194 ,  G06T2200/28

Abstract: A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row.

Abstract translation: 一种方法包括确定像素图的一行中的非零运行的位置和长度。 该方法还包括至少部分地基于位置和长度来确定前一行中的非零运行的数量的邻居。 另外，该方法至少部分地基于非零运行的第二邻居的对应关系图来更新非零运行的对应关系图和非零运行的第一邻居的对应关系图 响应于确定非零运行在前一行中具有至少两个邻居。

公开(公告)号：US20160034399A1

公开(公告)日：2016-02-04

申请号：US14450145

申请日：2014-08-01

Applicant: Analog Devices Technology

Inventor： Abhijit Giri ,  Saurbh Srivastava ,  Michael S. Allen

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F2212/1024

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract translation: 数字信号处理器通常在每个指令的两个操作数上操作，并且期望在一个周期内检索两个操作数。 一些数据高速缓存通过两个总线连接到处理器，并且内部使用两个或多个存储体来存储高速缓存行。 将高速缓存行分配给特定存储区基于高速缓存行关联的地址。 当两个内存访问映射到同一个存储区时，获取操作数会导致额外的延迟，因为访问是序列化的。 公开了一种用于提供无冲突双数据高速缓存访​​问的改进的银行组织 - 具有两个数据总线和两个存储体的基于总线的数据高速缓存系统。 每个存储体都作为相应数据总线的默认存储体。 只要访问的数据的两个值属于分配给两个相应的数据总线的两个单独的数据集，就避免了存储体冲突。

公开(公告)号：US09148168B2

公开(公告)日：2015-09-29

申请号：US14065732

申请日：2013-10-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhao Li ,  David Alldred

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/38 ,  H03M3/424 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。

公开(公告)号：US20150219721A1

公开(公告)日：2015-08-06

申请号：US14169667

申请日：2014-01-31

Applicant: Analog Devices Technology

Inventor： Hua-Jung Yang ,  Janne Klemetti

IPC: G01R31/36

CPC classification number: G01R31/3651 ,  G01R31/3624 ,  G01R31/3675 ,  H02J7/0016 ,  H02J7/0021 ,  H02J7/0031 ,  H02J7/0036 ,  H02J7/0073

Abstract: A device to determine a state of a battery is disclosed. One or more transistors provide a resistance between first and second nodes. The one or more transistors are configured to conduct a supply current from a battery between the first node and the second node. A measurement circuit measures the voltage generated between the first node and the second node. The measurement circuit further measures the supply voltage. A calculation circuit generates an estimate of the supply current based on the voltage measured between the first node and the second node and the resistance of the one or more transistors. The calculation circuit generates an estimate of the state of charge of the battery based on the measured supply voltage and the estimate of the supply current.

Abstract translation: 公开了一种确定电池状态的装置。 一个或多个晶体管提供第一和第二节点之间的电阻。 一个或多个晶体管被配置为在第一节点和第二节点之间从电池传导供电电流。 测量电路测量在第一节点和第二节点之间产生的电压。 测量电路进一步测量电源电压。 计算电路基于在第一节点和第二节点之间测量的电压和一个或多个晶体管的电阻来产生供电电流的估计。 计算电路基于所测量的电源电压和电源电流的估计，产生电池的充电状态的估计。

公开(公告)号：US09092429B2

公开(公告)日：2015-07-28

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/38

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US20150180485A1

公开(公告)日：2015-06-25

申请号：US14134767

申请日：2013-12-19

Applicant: Analog Devices Technology

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/099 ,  H03L7/093

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括具有调谐电压输入的VCO和被配置为设置VCO的频带设置的频率调谐电路。 频率调谐电路可以包括电压监视器，其被配置为将调谐电压输入的电压电平与一个或多个调谐电压阈值电平进行比较，控制电路被配置为至少控制VCO的频带设置和偏置电流设置， 以及振幅检测电路，被配置为将VCO的振荡信号的振幅与一个或多个振幅阈值电平进行比较。

公开(公告)号：US09065479B2

公开(公告)日：2015-06-23

申请号：US14214180

申请日：2014-03-14

Applicant: Analog Devices Technology

Inventor： Dennis A. Dempsey

IPC: H03M1/66 ,  H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/76

CPC classification number: H03M1/68 ,  H03M1/00 ,  H03M1/06 ,  H03M1/66 ,  H03M1/682 ,  H03M1/765

Abstract: In an example, a multistring DAC is described and includes at least two DAC stages. Each DAC stage includes a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC.

Abstract translation: 在一个示例中，描述了多段DAC并且包括至少两个DAC级。 每个DAC级包括一串阻抗元件和一个交换网络。 在一种配置中，多串DAC被配置为使第一串的端子处的电压变化与跨第一和第二串耦合的第一开关网络的电压降分开，以响应于数字输入而提供模拟输出 到DAC。