Injection phase locking device in an fm-transmitter for a self-oscillating oscillator modulated by a modulation signal
    153.
    发明授权
    Injection phase locking device in an fm-transmitter for a self-oscillating oscillator modulated by a modulation signal 失效
    用于由调制信号调制的自激振荡器的FM发射机中的注射相位锁定装置

    公开(公告)号:US3737777A

    公开(公告)日:1973-06-05

    申请号:US3737777D

    申请日:1971-07-02

    Inventor: ENDERSZ G

    CPC classification number: H03C3/09

    Abstract: A phase locking arrangement in which a free-running oscillator running with a frequency fo is injection phase locked by a synchronizing oscillator with a free-running frequency fs and a multiplier giving a multiplied frequency n . fs. A modulating frequency fm modulates both the free-running oscillator and the synchronizing oscillator through two direct coupled FMmodulators, so that the free-running oscillator will be continuously tuned to a frequency f1 which is chosen so that the synchronizing band Delta f f1 - fo of the free-running oscillator is narrow, so that the synchronizing power from the synchronizing oscillator can be kept low.

    Abstract translation: 一种锁相装置,其中以频率fo运行的自由振荡的振荡器通过具有自由运行频率fs的同步振荡器和产生倍频n的乘法器被注入锁相。 fs。 调制频率fm通过两个直接耦合的FM调制器对自由振荡器和同步振荡器进行调制,使得自由振荡器将被连续调谐到频率f1,频率f1被选择为使得同步带DELTA f = f1 自由振荡器的fo较窄,使得来自同步振荡器的同步功率可以保持较低。

    Arrangement for metallizing of parts of a body
    154.
    发明授权
    Arrangement for metallizing of parts of a body 失效
    用于金属部件的装配的装置

    公开(公告)号:US3696781A

    公开(公告)日:1972-10-10

    申请号:US3696781D

    申请日:1971-01-15

    CPC classification number: C23C2/00

    Abstract: Apparatus for metallizing parts of a body by dipping into molten metal includes a plurality of part vessels or dip tanks with different heights and widths so chosen in accordance with the parts of the body to be metallized.

    Abstract translation: 用于通过浸入熔融金属中来对身体的部分进行金属化的装置包括根据待金属化的身体部分选择的具有不同高度和宽度的多个部分血管或浸槽。

    Process control scanner apparatus
    155.
    发明授权
    Process control scanner apparatus 失效
    过程控制扫描仪设备

    公开(公告)号:US3673577A

    公开(公告)日:1972-06-27

    申请号:US3673577D

    申请日:1971-01-25

    CPC classification number: H04Q3/54591

    Abstract: A process control computer scans test points arranged in groups to perform operations in accordance with changes in the states of the test points. The data store of the computer stores the states of the test points as words wherein each work represents a group of test points and the bits of the words represent the test points of the group. A flag resister of the data store comprises a group of bit cells with each bit cell being associated with one of the words. During the scan if the change of state of a test point changes, the associated bit in the data store is changed and the flange bit of the associated word is marked. Thereafter, the computer need only scan those words whose flag bits have been marked.

    Abstract translation: 过程控制计算机扫描分组排列的测试点,以根据测试点状态的变化进行操作。 计算机的数据存储器将测试点的状态存储为单词,其中每个工作表示一组测试点,并且单词的位表示组的测试点。 数据存储器的标志寄存器包括一组位单元,其中每个位单元与一个单词相关联。 在扫描期间如果测试点的状态改变,数据存储器中的关联位被改变,并且相关联的字的法兰位被标记。 此后,计算机只需扫描标记位被标记的那些字。

    Radar unit arrangement for determining in received echo pulses the position of the pulse center and the pulse duration
    156.
    发明授权
    Radar unit arrangement for determining in received echo pulses the position of the pulse center and the pulse duration 失效
    用于确定接收到的ECHO的雷达单元布局脉冲脉冲中心的位置和脉冲持续时间

    公开(公告)号:US3660845A

    公开(公告)日:1972-05-02

    申请号:US3660845D

    申请日:1970-01-05

    CPC classification number: G04F10/04 G01S7/28

    Abstract: A radar unit arrangement for determining the position of the pulse center and the pulse duration of the received echo pulses. The echo pulses gate a number of subpulses to a first binary updown counter which counts the subpulses. A second binary up-down counter receives a pulse from the first each time a certain value is exceeded. A third binary counter indicates the time elapsed from the moment of the emitting a radar pulse. The contents of the second and the third binary counter are continuously compared in a comparator which each time equality is obtained activates a bistable circuit. The first and the second binary counters are controlled by the bistable circuit so as to switch the counting direction of the counter in such a way that the number of subpulses before and after the change of state of the bistable circuit will be the same.

    Abstract translation: 雷达单元布置,用于确定脉冲中心的位置和接收的回波脉冲的脉冲持续时间。 回波脉冲将多个子脉冲门控到计数子脉冲的第二个二进制递减计数器。 第二个二进制递增计数器每次超过某个值时从第一个二进制递增计数器接收脉冲。 第三个二进制计数器指示从发出雷达脉冲之时起经过的时间。 在比较器中连续地比较第二和第三二进制计数器的内容,每当获得相等性时,激活双稳态电路。 第一和第二二进制计数器由双稳态电路控制,以便以双稳态电路状态改变之前和之后的子脉冲数相同的方式切换计数器的计数方向。

    Phase detection circuit
    157.
    发明授权
    Phase detection circuit 失效
    相位检测电路

    公开(公告)号:US3659210A

    公开(公告)日:1972-04-25

    申请号:US3659210D

    申请日:1970-10-26

    CPC classification number: H03D13/008

    Abstract: Phase detection circuit, which in the state of a voltage value indicates the difference between the phase of an incoming signal and the phase of a reference signal. The circuit is built up by an operational amplifier with two inputs, one of them inverting the phase of the incoming signal. The incoming signal is fed to both inputs of the amplifier, whereby the signal is fed to the not inverting input via a switch which is controlled by the reference signal in such a manner that it alternatively lets through and blocks up the incoming signal during every other half period of the reference signal. The amplifier is so dimensioned that the amplification of signals fed to the inverting input is as high or lower than the amplification of signals fed to the other input.

    Abstract translation: 在电压值状态下的相位检测电路表示输入信号的相位与参考信号的相位之差。 该电路由具有两个输入的运算放大器构成,其中一个反相输入信号的相位。 输入信号被馈送到放大器的两个输入端,由此信号通过由参考信号控制的开关馈送到非反相输入端,使得它可以在每隔一个时间通过并阻塞输入信号 参考信号的半周期。 放大器的尺寸如此,使得馈送到反相输入端的信号的放大率高于或低于馈送到另一输入端的信号的放大。

    Combined loud- and low-speaking telephone instrument having two acoustic converters
    158.
    发明授权
    Combined loud- and low-speaking telephone instrument having two acoustic converters 失效
    具有双声道转换器的组合式低扬声器电话

    公开(公告)号:US3659050A

    公开(公告)日:1972-04-25

    申请号:US3659050D

    申请日:1970-10-22

    CPC classification number: H04M1/62 H04M1/0202 H04M1/6033

    Abstract: Combined loud- and low-speaking telephone instrument in one unit comprising no more than two electro-acoustic converters, one of which is used as a microphone when the telephone instrument is in its loud-speaking function position and as a telephone receiver when the instrument is in its low-speaking function position, while the other electro-acoustic converter is used as a loudspeaker when the telephone instrument is in its loud-speaking function position and as a microphone when the instrument is in its low-speaking function position. When resting on a table or a similar support a switch button which protrudes through the bottom of the telephone instrument is pressed in so as to keep this in its loud-speaking function position, and when the instrument is lifted from its support the switch button is pressed out switching the instrument to its low-speaking function position.

    Abstract translation: 组合的大声低声电话乐器在一个单元中,包括不超过两个电声转换器,当电话乐器处于其扬声功能位置时,其中一个用作麦克风,当仪器 处于低声功能位置,而当电话乐器处于扬声功能位置时,其他电声转换器用作扬声器,当乐器处于低声功能位置时用作麦克风 。 当放在桌子或类似的支架上时,通过按压电话乐器底部的开关按钮将其保持在扬声器的功能位置,当仪器从支架上抬起时,开关按钮为 按下将仪器切换到低位功能位置。

    Apparatus for identifying those means of a plurality of means which have changed state
    159.
    发明授权
    Apparatus for identifying those means of a plurality of means which have changed state 失效
    用于识别具有更改状态的多种手段的手段的装置

    公开(公告)号:US3653003A

    公开(公告)日:1972-03-28

    申请号:US3653003D

    申请日:1970-05-01

    CPC classification number: H04Q3/545

    Abstract: Apparatus for identifying those means of a plurality of means which have changed their binary state. A reference is sequentially obtained to only those means which have changed their state without spending unnecessary work sifting off the remaining means. The arrangement is particularly applicable in telecommunication systems, more especially such systems which have a central control, e.g., program store controlled systems in which the arrangement makes it possible to reduce considerably the idle load of a controlling computer.

    Abstract translation: 用于识别已经改变其二进制状态的多个装置的装置的装置。 依次获得参考,只有那些已经改变了他们的状态而不花费不必要的工作来筛选剩余的手段的手段。 该装置特别适用于电信系统,更具体地说,这种具有中央控制的系统,例如程序存储控制系统,其中该装置可以显着地减少控制计算机的空载。

    Rack for counters
    160.
    发明授权
    Rack for counters 失效
    柜台机架

    公开(公告)号:US3650587A

    公开(公告)日:1972-03-21

    申请号:US3650587D

    申请日:1970-04-06

    CPC classification number: H05K7/02 H04Q1/09 H04Q1/11

    Abstract: Rack for holding a plurality of counters in rows and columns. The rack comprises a number of casings, each with a rectangular bottom part divided into compartments the construction of which is made in such a way that it facilitates an easy pushing-in of a counter into a compartment. A single lid provided with windowopenings for reading of the counters protects all the counters in one casing. The casings are provided with hinges so that they can be swung out for connection or inspection.

    Abstract translation: 用于在行和列中保存多个计数器的机架。 机架包括多个壳体,每个壳体具有被分成隔室的矩形底部部分,隔室的构造以便于将柜台容易地推入隔间的方式制成。 设置有用于读取计数器的窗口的单个盖子保护一个外壳中的所有计数器。 外壳设有铰链,使其可以摆出来连接或检查。

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