公开(公告)号：US06420221B1

公开(公告)日：2002-07-16

申请号：US09507646

申请日：2000-02-22

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

IPC: H01L218238

CPC classification number: H01L21/823878 ,  H01L27/0921

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

Abstract translation: 通过将p +和n +扩散保护环分别插入到半导体衬底的NMOS和PMOS源极侧中，分别描述了通过插入 - 免疫的CMOS I / O结构。 P +扩散保护环围绕各个n沟道晶体管，n +扩散保护环围绕着单独的p沟道晶体管。 连接到电源的这些保护环通过p型衬底到p +保护环或n阱到n +保护环，降低了与CMOS结构通常相关的寄生SCR的分流电阻。 在第二优选实施例中，将深p +注入植入到p +保护环或p阱拾取器中以降低寄生SCR的分流电阻。 与第一优选实施例的保护环相同的n +和p +保护环分别连接到正和负电压源。 在两个优选实施例中的任一个中，减小的分流电阻防止SCR的寄生双极晶体管的正向偏置，从而确保保持电压大于电源电压。

公开(公告)号：US5903499A

公开(公告)日：1999-05-11

申请号：US928227

申请日：1997-09-12

Applicant: Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chou Ho

Inventor： Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.

Abstract translation: 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是首先向EEPROM单元的源极施加适度高的正电压脉冲。 同时，向控制栅极施加第一相对较大的负电压。 同时对半导体衬底施加接地参考电位。 在同一时间，排水沟漂浮。 然后通过漂浮源极和漏极并将接地参考电位施加到半导体衬底来去除快闪EEPROM单元。 同时，向控制栅极施加第二相对大的负电压脉冲。

公开(公告)号：US5838618A

公开(公告)日：1998-11-17

申请号：US927472

申请日：1997-09-11

Applicant: Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

Inventor： Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/04 ,  G11C7/00

CPC classification number: G11C16/14

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.

Abstract translation: 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。 通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。 同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。 擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。 源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。

公开(公告)号：US5565790A

公开(公告)日：1996-10-15

申请号：US387084

申请日：1995-02-13

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/62

CPC classification number: H01L27/0266 ,  H01L27/0251

Abstract: An improved ESD protection circuit of the type having a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and a node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.

Abstract translation: 一种改进的ESD保护电路，其具有连接在接地和待保护的焊盘之间的钳位的场晶体管，以及连接在地和被保护电路连接的节点之间的FET触发电路。 电阻器使焊盘和节点互连。 当高ESD电压引起雪崩击穿时，触发FET导通，并且来自触发FET的电荷载流子导通场晶体管钳位。 在场晶体管钳位导通之前，FET的栅极氧化物发生氧化物击穿。 电阻器连接在栅电极和地之间以限制在雪崩发展的时间期间通过氧化物的电流，并且钳位器导通。

公开(公告)号：US08018000B2

公开(公告)日：2011-09-13

申请号：US12046216

申请日：2008-03-11

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

IPC: H01L23/62

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42368

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract translation: 公开了高压半导体器件中的静电放电（ESD）保护，其通过产生围绕漏极或源极的隔离岛来提供晶体管漏极或源极之间的增强的电流隔离。 该隔离岛可以是漏极/源极所在的较高掺杂区域。 该岛区域和周围基板的较高掺杂之间的结点用于限制通过漏极/源极的电流量。 另外，可以使用氧化物特征来形成围绕漏极/源极接触的岛。 再次，这种隔离效应使得穿过器件的电流量更均匀，这保护了器件免受ESD事件的损害。

公开(公告)号：US07583484B2

公开(公告)日：2009-09-01

申请号：US10644718

申请日：2003-08-20

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H02H3/22

CPC classification number: H01L27/0285

Abstract: A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.

Abstract translation: 用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。 传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。 该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

公开(公告)号：US20090179270A1

公开(公告)日：2009-07-16

申请号：US12046216

申请日：2008-03-11

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yung-Tien Tsai ,  Anthony Oates

IPC: H01L23/62 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42368

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract translation: 公开了高压半导体器件中的静电放电（ESD）保护，其通过产生围绕漏极或源极的隔离岛来提供晶体管漏极或源极之间的增强的电流隔离。 该隔离岛可以是漏极/源极所在的较高掺杂区域。 该岛区域和周围基板的较高掺杂之间的结点用于限制通过漏极/源极的电流量。 另外，可以使用氧化物特征来形成围绕漏极/源极接触的岛。 再次，这种隔离效应使得穿过器件的电流量更均匀，这保护了器件免受ESD事件的损害。

公开(公告)号：US07485905B2

公开(公告)日：2009-02-03

申请号：US11459650

申请日：2006-07-25

Applicant: Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

Inventor： Feng-Chi Hung ,  Jian-Hsing Lee ,  Hung-Lin Chen ,  Deng-Shun Chang

IPC: H01L29/80 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0692 ,  H01L29/7835

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Abstract translation: 一种静电放电保护装置，包括多指门，具有第二导电性的第一轻掺杂区，第二导电性的第一重掺杂区和第二导电性的第二轻掺杂区。 多指门包括在第一导电性的有源区域上并联连接的多个指状物。 第二导电性的第一轻掺杂区域设置在半导体衬底中并且在两个指状物之间。 第二导电性的第一重掺杂区域设置在第二导电性的第一轻掺杂区域中。 第二导电性的第二轻掺杂区域位于第二导电性的第一轻掺杂区域的下方并与其邻接。

公开(公告)号：US20090008710A1

公开(公告)日：2009-01-08

申请号：US11773364

申请日：2007-07-03

Applicant: Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

Inventor： Chi-San Wei ,  Kuo-Ming Wu ,  Jian-Hsing Lee

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878

Abstract: A semiconductor device includes a gate electrode over a semiconductor substrate, wherein the gate electrode has a gate width direction; a source/drain region in the semiconductor substrate and adjacent the gate electrode, wherein the source/drain region has a first width in a direction parallel to the gate width direction; and a bulk pick-up region in the semiconductor substrate and abutting the source/drain region. The bulk pick-up region and the source/drain region have opposite conductivity types. The bulk pick-up region has a second width in the width direction, and wherein the second width is substantially less than the first width.

Abstract translation: 半导体器件包括在半导体衬底上的栅电极，其中栅电极具有栅极宽度方向; 在所述半导体衬底中并且与所述栅电极相邻的源极/漏极区域，其中所述源极/漏极区域在平行于所述栅极宽度方向的方向上具有第一宽度; 以及半导体衬底中的块体拾取区域并且邻接源极/漏极区域。 本体拾取区域和源极/漏极区域具有相反的导电类型。 本体拾取区域在宽度方向上具有第二宽度，并且其中第二宽度基本上小于第一宽度。

公开(公告)号：US07462885B2

公开(公告)日：2008-12-09

申请号：US11606424

申请日：2006-11-30

Applicant: Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

Inventor： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

IPC: H01L29/72 ,  H01L23/62

CPC classification number: H01L29/0847 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

Abstract translation: 公开了一种静电放电保护的MOS结构。 静电放电保护的MOS结构包括第一类型的半导体衬底，形成在半导体衬底中的第一类型的第一阱和与第一阱相邻布置的第二类型的第二阱。 MOS结构还包括用于形成MOS结构的栅电极的源极区，漏极区和氧化物层以及多晶硅层。 此外，MOS结构包括至少包括寄生NPN双极晶体管和插入在第二阱和半导体衬底之间的第二类型的掩埋层的寄生SCR。 掩埋层用于在ESD事件期间降低半导体衬底的电阻，使得由寄生SCR产生的ESD电流通过掩埋层和半导体衬底消散，从而保护MOS结构。