公开(公告)号：US06838352B1

公开(公告)日：2005-01-04

申请号：US10190459

申请日：2002-07-05

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/20

CPC classification number: H01L28/75 ,  H01L21/76807 ,  H01L23/5223

Abstract: A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.

Abstract translation: 公开了一种在半导体衬底上制造电容器的方法。 该方法可以包括同时形成至少一个通孔和至少一个上电容器板开口，该第一电介质层具有沉积在具有导电区域内的第一导电材料的第一材料区域上的底层盖电介质层，并且形成在 通过。 该方法还可以包括用第二导电材料填充通孔，沟槽和上电容器板开口，得到集成电路结构，并采用CMP从集成电路结构中去除任何多余的第二导电材料。

公开(公告)号：US06809863B2

公开(公告)日：2004-10-26

申请号：US10016166

申请日：2001-11-30

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: G02B530

CPC classification number: G02B5/3083 ,  Y10S359/90

Abstract: A low dispersion comb filter or interleaver assembly has a first interleaver element and a second interleaver element. The first interleaver element is configured so as to provide a dispersion vs. wavelength curve wherein each dispersion value thereof is approximately opposite in value to a dispersion value at the same wavelength for the second interleaver element, so as to mitigate net or total dispersion in the interleaver assembly.

Abstract translation: 低色散梳状滤波器或交织器组件具有第一交织器元件和第二交织器元件。 第一交织器元件被配置为提供色散相对于波长曲线，其中其每个色散值与第二交织器元件的相同波长处的色散值几乎相反，以便减轻第二交织器元件中的净色散或总色散 交织器装配。

公开(公告)号：US06787911B1

公开(公告)日：2004-09-07

申请号：US09317536

申请日：1999-05-24

Applicant: Bin Zhao ,  Maureen R. Brongo

Inventor： Bin Zhao ,  Maureen R. Brongo

IPC: H01L2348

CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76834

Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A look material is then deposited to fill the gaps bet n metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A prove layer is deposited on top of the metal lines and the look material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photoresist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

Abstract translation: 提供了一种用于在半导体本体上形成改进的互连结构的方法。 第一金属层沉积在半导体本体上。 具有高度的牺牲层沉积在第一金属层上。 牺牲层和金属层被图案化以形成分离的金属线，牺牲层保留在所述金属线上。 然后沉积外观材料以填充金属线上的间隙并覆盖牺牲层。 然后将低k材料去除到牺牲层的高度内的水平。 然后去除牺牲层。 证明层沉积在金属线和外观材料的顶部。 介电层沉积在保护层上。 保护层保护低k材料免受后续工艺步骤所用化学品的侵蚀，以蚀刻电介质层中的通孔，剥离光致抗蚀剂，并清洁通孔。 然后选择性地蚀刻保护层以使通孔塞和金属线之间的接触。

公开(公告)号：US06782158B2

公开(公告)日：2004-08-24

申请号：US10263988

申请日：2002-10-02

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: G02B628

CPC classification number: G02B6/29355 ,  G02B6/29386 ,  H04J14/02

Abstract: A dispersion mitigating interleaver assembly has a first unbalanced Mach-Zehnder interferometer (MZI) assembly which includes first and second output ports and which has first transmission vs. wavelength curve and a first dispersion vs. wavelength curve. The dispersion mitigating interleaver assembly also includes a second unbalanced MZI assembly which has a second transmission vs. wavelength curve and a second dispersion vs. wavelength curve. The second unbalanced MZI assembly receives an output from one of the first and second output ports of the first unbalanced MZI assembly. The second transmission vs. wavelength curve is substantially the same as the first transmission vs. wavelength curve and the second dispersion vs. wavelength curve is substantially opposite with respect to the first dispersion vs. wavelength curve, such that dispersion is substantially cancelled by the cooperation of the first and second unbalanced MZI assemblies.

公开(公告)号：US06444136B1

公开(公告)日：2002-09-03

申请号：US09559292

申请日：2000-04-25

Applicant: Q. Z. Liu ,  Bin Zhao

Inventor： Q. Z. Liu ,  Bin Zhao

IPC: B44C122

CPC classification number: H01L21/02134 ,  H01L21/02351 ,  H01L21/31058 ,  H01L21/3124 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76831

Abstract: Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure. All the disclosed embodiments can be practiced by exposing the low-k dielectric material to ion beams instead of electron beams.

Abstract translation: 公开了改进的低k电介质结构的制造。 制造低k电介质结构，同时克服与使用低k电介质材料相关的其他现有问题。 在一个实施例中，通过将低k电介质材料暴露于电子束来修改低k电介质材料的物理性质。 低k电介质材料的暴露部分变得更容易蚀刻和清洁，并且表现出更大的机械强度和减少吸湿性。 在另一个实施例中，执行多个增量曝光和蚀刻步骤以制造期望的结构。 在另一个实施例中，将低k电介质材料的曝光步骤与蚀刻步骤组合。 在同一系统中同时进行低k电介质材料的曝光和蚀刻。 在另一个实施例中，利用单次曝光和单个蚀刻步骤来制造所需的结构。 所有公开的实施例可以通过将低k电介质材料暴露于离子束而不是电子束来实施。

公开(公告)号：US06329290B1

公开(公告)日：2001-12-11

申请号：US09512396

申请日：2000-02-24

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H01L21311

CPC classification number: H01L21/76831 ,  H01L21/76808

Abstract: A via is first etched in a dielectric. Then a conformal layer is deposited over the dielectric and the via to reduce an initial width of the via to a target width. A trench is then etched in the dielectric and the conformal layer. Since the width of the via is reduced from the initial width to the target width, the resulting final via has a high aspect ratio. The via and the trench are then filled with metal which contacts an interconnect metal situated below the via. In one embodiment, copper is used to fill the via and the trench and also as the interconnect metal below the via. In one embodiment, the dielectric is silicon dioxide or fluorinated silicon dioxide and the conformal layer is silicon dioxide. In another embodiment, the dielectric is silicon dioxide or fluorinated silicon dioxide while the conformal layer is silicon nitride. To etch the trench in the dielectric and the conformal layer, a timed exposure to a carbon fluoride based plasma is employed. Alternatively, instead of timing the exposure to plasma, a suitable etch stop layer is used. In the embodiment where a conformal layer of high dielectric constant is used, the conformal layer remaining on the dielectric surface is removed using either chemical mechanical polishing or by plasma etching. The final structure is a via and a trench where the via's side walls are covered by the conformal layer while the trench's side walls are not covered by the conformal layer.

Abstract translation: 首先在电介质中蚀刻通孔。 然后在电介质和通孔上沉积保形层以将通孔的初始宽度减小到目标宽度。 然后在电介质和保形层中蚀刻沟槽。 由于通孔的宽度从初始宽度减小到目标宽度，所得到的最终通孔具有高纵横比。 然后，通孔和沟槽填充有与位于通孔下方的互连金属接触的金属。 在一个实施例中，铜用于填充通孔和沟槽，并且还用作通孔下方的互连金属。 在一个实施例中，电介质是二氧化硅或氟化二氧化硅，并且保形层是二氧化硅。 在另一个实施例中，电介质是二氧化硅或氟化二氧化硅，而保形层是氮化硅。 为了蚀刻电介质和共形层中的沟槽，采用了基于氟化碳的等离子体的定时曝光。 或者，代替等离子体曝光的定时，使用合适的蚀刻停止层。 在使用高介电常数的保形层的实施例中，使用化学机械抛光或通过等离子体蚀刻来去除保留在电介质表面上的保形层。 最终结构是通孔和沟槽，其中通孔的侧壁被保形层覆盖，而沟槽的侧壁不被保形层覆盖。