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    Method of forming dual-damascene interconnect structures employing low-k dielectric materials
    1.
    发明授权
    Method of forming dual-damascene interconnect structures employing low-k dielectric materials 有权
    使用低k电介质材料形成双镶嵌互连结构的方法

    公开(公告)号：US06627539B1

    公开(公告)日：2003-09-30

    申请号：US09149910

    申请日：1998-09-09

    Applicant: Bin Zhao ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Maureen R. Brongo

    IPC: H01L2144

    CPC classification number: H01L23/5329 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Interconnects in sub-micron and sub-half-micron integrated circuit devices are fabricated using a dual damascene process incorporating a low-k dielectric. A dual-damascene structure can be implemented without the necessity of building a single damascene base, and without CMP of the low-k dielectric. This structure simplifies the manufacturing process, reduces cost, and effectively reduces intra-level and inter-level capacitance, resistivity, and noise related to substrate coupling. In accordance with a further aspect of the present invention, a modified silicon oxide material such as silsesquioxane is used for the low-k dielectric in conjunction with silicon dioxide cap layers, allowing an improved process window and simplifying the etching process.

    Abstract translation: 使用包含低k电介质的双镶嵌工艺制造亚微米和亚半微米集成电路器件中的互连。 可以实现双镶嵌结构，而不需要构建单个镶嵌基底，并且不需要低k电介质的CMP。 该结构简化了制造工艺，降低了成本，并且有效地降低了与衬底耦合有关的电平，电平和电平以及噪声。 根据本发明的另一方面，与二氧化硅盖层结合使用改性氧化硅材料如倍半硅氧烷用于低k电介质，允许改进的工艺窗口并简化蚀刻工艺。

    Fabrication of high-density capacitors for mixed signal/RF circuits
    2.
    发明授权
    Fabrication of high-density capacitors for mixed signal/RF circuits 有权
    用于混合信号/ RF电路的高密度电容器的制造

    公开(公告)号：US07060557B1

    公开(公告)日：2006-06-13

    申请号：US10190297

    申请日：2002-07-05

    Applicant: Bin Zhao ,  Qizhi Liu ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Qizhi Liu ,  Maureen R. Brongo

    IPC: H01L21/8242

    CPC classification number: H01L28/91

    Abstract: A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The underlying cap dielectric layer may be modified in a way that increases its dielectric constant as a result of simultaneously be heated by a heat source and impinged with and energy beam. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.

    Abstract translation: 公开了一种在半导体衬底上制造电容器的方法。 该方法可以包括同时形成至少一个通孔和至少一个上电容器板开口，该第一电介质层具有沉积在具有导电区域内的第一导电材料的第一材料区域上的底层盖电介质层，并且形成在 通过。 底层盖电介质层可以以增加其介电常数的方式进行修改，这是由于同时被热源加热并与其碰撞而产生的能量束。 该方法还可以包括用第二导电材料填充通孔，沟槽和上电容器板开口，得到集成电路结构，并采用CMP从集成电路结构中去除任何多余的第二导电材料。

    Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
    3.
    发明授权
    Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing 有权
    与半导体集成电路制造的低介电常数绝缘体互连

    公开(公告)号：US06187672B1

    公开(公告)日：2001-02-13

    申请号：US09158337

    申请日：1998-09-22

    Applicant: Bin Zhao ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Maureen R. Brongo

    IPC: H01L214763

    CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76834

    Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

    Abstract translation: 提供了一种用于在半导体本体上形成改进的互连结构的方法。 第一金属层沉积在半导体本体上。 具有高度的牺牲层沉积在第一金属层上。 牺牲层和金属层被图案化以形成分离的金属线，牺牲层保留在所述金属线上。 然后沉积低k材料以填充金属线之间的间隙并覆盖牺牲层。 然后将低k材料去除到牺牲层的高度内的水平。 然后去除牺牲层。 保护层沉积在金属线和低k材料的顶部。 介电层沉积在保护层上。 保护层保护低k材料免受后续工艺步骤所用化学品的侵蚀，以蚀刻电介质层中的通孔，剥离光致抗蚀剂和清洁通孔。 然后选择性地蚀刻保护层以使通孔塞和金属线之间的接触。

    Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
    4.
    发明授权
    Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing 有权
    与半导体集成电路制造的低介电常数绝缘体互连

    公开(公告)号：US06787911B1

    公开(公告)日：2004-09-07

    申请号：US09317536

    申请日：1999-05-24

    Applicant: Bin Zhao ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Maureen R. Brongo

    IPC: H01L2348

    CPC classification number: H01L21/76802 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76834

    Abstract: A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A look material is then deposited to fill the gaps bet n metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A prove layer is deposited on top of the metal lines and the look material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photoresist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

    Abstract translation: 提供了一种用于在半导体本体上形成改进的互连结构的方法。 第一金属层沉积在半导体本体上。 具有高度的牺牲层沉积在第一金属层上。 牺牲层和金属层被图案化以形成分离的金属线，牺牲层保留在所述金属线上。 然后沉积外观材料以填充金属线上的间隙并覆盖牺牲层。 然后将低k材料去除到牺牲层的高度内的水平。 然后去除牺牲层。 证明层沉积在金属线和外观材料的顶部。 介电层沉积在保护层上。 保护层保护低k材料免受后续工艺步骤所用化学品的侵蚀，以蚀刻电介质层中的通孔，剥离光致抗蚀剂，并清洁通孔。 然后选择性地蚀刻保护层以使通孔塞和金属线之间的接触。

    Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials
    6.
    发明授权
    Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials 有权
    使用电子束的双镶嵌工艺和低介电常数材料的离子注入固化方法

    公开(公告)号：US06271127B1

    公开(公告)日：2001-08-07

    申请号：US09329569

    申请日：1999-06-10

    Applicant: Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

    Inventor： Qizhi Liu ,  David Feiler ,  Bin Zhao ,  Maureen R. Brongo

    IPC: H01L214763

    CPC classification number: H01L21/76829 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76825 ,  Y10S438/949

    Abstract: Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.

    Abstract translation: 用于半导体工件的双镶嵌金属化的方法，其使用在绝缘体中产生蚀刻停止的工艺，从而消除了沉积蚀刻停止层的需要。 使用电子束曝光来固化绝缘体或具有低介电常数的材料。 将电子束应用于低介电常数材料将低介电常数材料的最上层转化为蚀刻停止层，同时快速热加热固化低介电常数材料的其余部分。 在低介电常数材料中形成蚀刻停止层也可以通过使用离子注入固化低介电常数材料来实现。

    IC interconnect structures and methods for making same
    7.
    发明授权
    IC interconnect structures and methods for making same 有权
    IC互连结构及其制造方法

    公开(公告)号：US06245663B1

    公开(公告)日：2001-06-12

    申请号：US09163967

    申请日：1998-09-30

    Applicant: Bin Zhao ,  Maureen R. Brongo

    Inventor： Bin Zhao ,  Maureen R. Brongo

    IPC: H01L214763

    CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.

    Abstract translation: 公开了使用单个镶嵌工艺制造的亚微米级和次级半微米集成电路器件中的高级互连的方法和结构。 在先前的金属化层（例如，导电插头）的CMP处理之前而不是之前沉积介电蚀刻停止层（例如，氮化硅）。 该方案有效地消除了CMP腐蚀对蚀刻停止层的影响，因此允许使用极薄的蚀刻停止。 此外，可以获得沟槽蚀刻的高蚀刻选择性，并且从互连金属下方去除所有蚀刻停止材料，从而减少寄生效应。 图案化的介电层用作代替标准覆盖氮化硅层的金属盖，从而防止与被捕获的湿气和气体相关联的起泡和气泡的形成，并减少互连电容。

    Pulse width modulation with effective high duty resolution
    10.
    发明授权
    Pulse width modulation with effective high duty resolution 有权
    具有高占空比分辨率的脉宽调制

    公开(公告)号：US09490792B2

    公开(公告)日：2016-11-08

    申请号：US12703239

    申请日：2010-02-10

    Applicant: Bin Zhao

    Inventor： Bin Zhao

    IPC: H03K7/08 ,  H04N9/31 ,  H05B33/08 ,  H02M1/084

    CPC classification number: H03K7/08 ,  H02M1/084 ,  H04N9/3123 ,  H05B33/0818 ,  H05B33/0845 ,  Y02B20/346

    Abstract: A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The PWM signal generator receives an N-bit value representing a duty to be implemented and sets values X and Y to the M least significant bits and the N-M most significant bits, respectively, of the N-bit value. The value M can be determined based on the value N and a maximum implementable frequency of a clock signal used to time the generation of each PWM cycle. The PWM signal generator generates a cycle window of 2M PWM cycles, each PWM cycle of the cycle window having a duty of either Y or Y+1. The number of PWM cycles in the cycle window having the duty Y+1 is based on the value X and the PWM cycles having a particular duty are contiguous within the cycle window.

    Abstract translation: 脉冲宽度调制（PWM）信号发生器产生对于相应的周期窗口具有指定的有效PWM占空比分辨率的PWM信号。 PWM信号发生器接收表示要实现的占空比的N位值，并将值X和Y分别设置为N位值的M个最低有效位和N-M个最高有效位。 可以基于用于时间产生每个PWM周期的时钟信号的值N和最大可实施频率来确定值M. PWM信号发生器产生2M个PWM周期的周期窗口，周期窗口的每个PWM周期具有Y或Y + 1的占空比。 具有占空比Y + 1的周期窗口中的PWM周期的数量基于值X，并且具有特定占空比的PWM周期在周期窗口内是连续的。

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