公开(公告)号：US20210365364A1

公开(公告)日：2021-11-25

申请号：US17397393

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Christian M. Gyllenskog ,  Jonathan Scott Parry ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.

公开(公告)号：US11157404B2

公开(公告)日：2021-10-26

申请号：US16552246

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz

IPC: G06F12/08 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for remapping data of flash memory indexed by logical block addresses (LBAs) of a host device in response to re-map requests received at a flash memory system from the host device or in response to re-map requests generated at the flash memory system.

公开(公告)号：US20210326257A1

公开(公告)日：2021-10-21

申请号：US17306419

申请日：2021-05-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/0804

Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.

公开(公告)号：US11074177B2

公开(公告)日：2021-07-27

申请号：US16445738

申请日：2019-06-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a host write activity are described. A host write progress can be represented by an actual host write count relative to a target host write count. The host write activity may be estimated in a unit time such as per day, or accumulated over a specified time period. A memory controller can adjust an amount of memory space to be freed by a GC operation according to the host write progress. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the host write progress.

公开(公告)号：US20210200698A1

公开(公告)日：2021-07-01

申请号：US17111195

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Christian M. Gyllenskog ,  David Aaron Palmer

IPC: G06F13/16 ,  G06F13/24 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0868

Abstract: Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

公开(公告)号：US20210124530A1

公开(公告)日：2021-04-29

申请号：US17140839

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.

公开(公告)号：US20210089444A1

公开(公告)日：2021-03-25

申请号：US17118152

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/02 ,  G11C11/16 ,  G11C16/10

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window.

公开(公告)号：US20210064465A1

公开(公告)日：2021-03-04

申请号：US17020430

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/10 ,  H03M13/29

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

公开(公告)号：US10930354B2

公开(公告)日：2021-02-23

申请号：US16799490

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/08 ,  G11C16/16 ,  G11C16/08 ,  G06F3/06 ,  G11C7/10

Abstract: Devices and techniques for enhanced flush transfer efficiency via flush prediction in a storage device are described herein. User data from a user data write can be stored in a buffer. The size of the user data stored in the buffer can be smaller than a write width for a storage device subject to the write. This size difference results in buffer free space. A flush trigger can be predicted. Additional data can be marshaled in response to the prediction of the flush trigger. The size of the additional data is less than or equal to the buffer free space. The additional data can be stored in the buffer free space. The contents of the buffer can be written to the storage device in response to the flush trigger.

公开(公告)号：US20200209944A1

公开(公告)日：2020-07-02

申请号：US16293295

申请日：2019-03-05

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F1/3234 ,  G06F1/3225 ,  G06F9/54 ,  G06F9/38

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include receiving an operation change indication for a NAND memory operation at power management circuitry of a NAND memory system, and summing a power credit to a value of a first register associated with the operation change indication to provide an indication of instantaneous power consumption of the NAND memory system as the value of the first register.