公开(公告)号：US09590102B2

公开(公告)日：2017-03-07

申请号：US14687815

申请日：2015-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Wai-Yi Lien

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/51 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02524 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/7624 ,  H01L29/0638 ,  H01L29/1604 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/401 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

Abstract translation: 一种制造半导体器件的方法包括形成鳍结构，其包括阱层，设置在阱层上的氧化物层和设置在氧化物层上的沟道层。 形成隔离绝缘层，使得翅片结构的沟道层从隔离绝缘层突出，并且氧化物层的一部分或全部被嵌入隔离绝缘层中。 在鳍结构上形成栅结构。 通过蚀刻未被栅极结构覆盖的鳍状结构的一部分使得氧化物层露出而形成凹部。 在暴露的氧化物层中形成凹部。 在氧化物层的凹部中的外延籽晶层。 在凹部内和上方形成外延层。 外延层与外延种子层接触。

公开(公告)号：US09496397B2

公开(公告)日：2016-11-15

申请号：US13970790

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L21/76 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76 ,  H01L21/76229 ,  H01L29/66795

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having epitaxial enhancement structures, and an associated method of fabrication. In some embodiments, the FinFET device has a semiconductor substrate having a plurality of isolation regions overlying the semiconductor substrate. A plurality of three-dimensional fins protrude from a top surface of the semiconductor substrate at locations between the plurality of isolation regions. Respective three-dimensional fins have an epitaxial enhancement structure that introduces a strain into the three-dimensional fin. The epitaxial enhancement structures are disposed over a semiconductor material within the three-dimensional fin at a position that is more than 10 nanometers above a bottom of an adjacent isolation region. Forming the epitaxial enhancement structure at such a position provides for sufficient structural support to avoid isolation region collapse.

Abstract translation: 本公开涉及具有外延增强结构的Fin场效应晶体管（FinFET）器件及其相关制造方法。 在一些实施例中，FinFET器件具有半导体衬底，其具有覆盖半导体衬底的多个隔离区域。 在多个隔离区域之间的位置处，多个三维翅片从半导体衬底的顶表面突出。 相应的三维翅片具有向三维翅片引入应变的外延增强结构。 外延增强结构被布置在三维鳍片内的半导体材料上方，位于相邻隔离区域的底部之上超过10纳米的位置。 在这样的位置形成外延增强结构提供足够的结构支撑以避免隔离区域崩溃。

公开(公告)号：US20150028426A1

公开(公告)日：2015-01-29

申请号：US13952753

申请日：2013-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Gwan Sin Chang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849

Abstract: The present disclosure relates to a Fin field effect transistor (FinFET) device having a buried silicon germanium oxide structure configured to enhance performance of the FinFET device. In some embodiments, the FinFET device has a three-dimensional fin of semiconductor material protruding from a substrate at a position located between first and second isolation regions. A gate structure overlies the three-dimensional fin of semiconductor material. The gate structure controls the flow of charge carriers within the three-dimensional fin of semiconductor material. A buried silicon-germanium-oxide (SiGeOx) structure is disposed within the three-dimensional fin of semiconductor material at a position extending between the first and second isolation regions.

Abstract translation: 本公开涉及具有被配置为增强FinFET器件的性能的掩埋硅锗氧化物结构的Fin场效应晶体管（FinFET）器件。 在一些实施例中，FinFET器件具有在位于第一和第二隔离区域之间的位置处从衬底突出的半导体材料的三维鳍。 栅极结构覆盖半导体材料的三维鳍。 栅极结构控制半导体材料的三维鳍内的电荷载流子的流动。 掩埋的硅 - 锗氧化物（SiGeOx）结构设置在半导体材料的三维翅片内，在第一和第二隔离区域之间延伸的位置。