公开(公告)号：US20230157029A1

公开(公告)日：2023-05-18

申请号：US17548607

申请日：2021-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

公开(公告)号：US20230066509A1

公开(公告)日：2023-03-02

申请号：US17491509

申请日：2021-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Hon-Huei Liu ,  Chun-Hsien Lin

IPC: H01L27/11507 ,  H01L27/12 ,  H01L27/13

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

公开(公告)号：US20230009982A1

公开(公告)日：2023-01-12

申请号：US17393407

申请日：2021-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hon-Huei Liu ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H03H3/08 ,  H03H9/02

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

公开(公告)号：US20220262687A1

公开(公告)日：2022-08-18

申请号：US17737031

申请日：2022-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region, removing part of the first fin-shaped structure to form a first trench, forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure, forming a first gate structure and a second gate structure on the DDB structure as a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure, and forming a contact plug between the first gate structure and the second gate structure on the DDB structure.

公开(公告)号：US20220223728A1

公开(公告)日：2022-07-14

申请号：US17706553

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

公开(公告)号：US10658458B2

公开(公告)日：2020-05-19

申请号：US16028386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Chun-Hsien Lin ,  Wen-An Liang

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.

公开(公告)号：US10475892B2

公开(公告)日：2019-11-12

申请号：US16172851

申请日：2018-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739

Abstract: A method for forming a tunneling field effect transistor is disclosed, which includes the following steps. First, a semiconductor substrate is provided. A source region is formed on the semiconductor substrate. A tunneling region having a sidewall and a top surface is formed on the source region. A drain region is formed on the tunneling region. A gate dielectric layer is then formed, covering the sidewall and the top surface of the tunneling region. A first metal layer is formed, covering the gate dielectric layer. Subsequently, an anisotropic etching process is performed to remove a portion of the first metal layer. After the anisotropic etching process, a second metal layer is fabricated to cover the remaining first metal layer and the gate dielectric layer.

公开(公告)号：US10468517B2

公开(公告)日：2019-11-05

申请号：US15691779

申请日：2017-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/20 ,  H01L29/739

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US20190279909A1

公开(公告)日：2019-09-12

申请号：US16416279

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Chun-Hsien Lin ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC: H01L21/8234 ,  H01L21/30 ,  H01L21/321 ,  H01L21/28

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

公开(公告)号：US20190259762A1

公开(公告)日：2019-08-22

申请号：US16402137

申请日：2019-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Yu-Ru Yang ,  Chih-Chien Liu ,  Chao-Ching Hsieh ,  Chun-Hsien Lin

IPC: H01L27/105 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10 ,  H01L23/528 ,  H01L43/02

Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.