公开(公告)号：US20230135072A1

公开(公告)日：2023-05-04

申请号：US18090510

申请日：2022-12-29

申请人： United Microelectronics Corp.

发明人： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

摘要： The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US20210151666A1

公开(公告)日：2021-05-20

申请号：US17141194

申请日：2021-01-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC分类号： H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

摘要： A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US10103250B2

公开(公告)日：2018-10-16

申请号：US15677029

申请日：2017-08-15

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/265 ,  H01L21/768

摘要： A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US09985123B2

公开(公告)日：2018-05-29

申请号：US15602087

申请日：2017-05-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC分类号： H01L29/78 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US09773890B2

公开(公告)日：2017-09-26

申请号：US14919716

申请日：2015-10-21

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/26513 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US20170263744A1

公开(公告)日：2017-09-14

申请号：US15602087

申请日：2017-05-22

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC分类号： H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US09711411B2

公开(公告)日：2017-07-18

申请号：US14963216

申请日：2015-12-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Shih-Fang Tzou ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC分类号： H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/823431 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/31116 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

公开(公告)号：US09698255B2

公开(公告)日：2017-07-04

申请号：US14681119

申请日：2015-04-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC分类号： H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US20160268203A1

公开(公告)日：2016-09-15

申请号：US14681119

申请日：2015-04-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC分类号： H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3115 ,  H01L21/311

CPC分类号： H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层，其中栅极结构包括其上的硬掩模; 在栅极结构和ILD层上形成介电层; 去除介电层的一部分以暴露硬掩模和ILD层; 并进行表面处理以在硬掩模和ILD层中形成掺杂区域。

公开(公告)号：US11862727B2

公开(公告)日：2024-01-02

申请号：US18090510

申请日：2022-12-29

申请人： United Microelectronics Corp.

发明人： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L29/7854 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66818

摘要： The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.