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    Method for manufacturing a micromechanical component, and micromechanical component
    151.
    发明授权
    Method for manufacturing a micromechanical component, and micromechanical component 有权
    微机械部件的制造方法以及微机电部件

    公开(公告)号：US08687255B2

    公开(公告)日：2014-04-01

    申请号：US13057411

    申请日：2009-07-06

    Applicant: Stefan Finkbeiner ,  Tjalf Pirk ,  Christoph Friese

    Inventor： Stefan Finkbeiner ,  Tjalf Pirk ,  Christoph Friese

    IPC: G02B26/08

    CPC classification number: B81C1/00166 ,  B81B2201/033 ,  B81C2201/014

    Abstract: A method for manufacturing a micromechanical component is described, including the steps of: forming a first etch stop layer on a base substrate, the first etch stop layer being formed in such a way that it has a first pattern of through-cutouts; forming a first electrode-material layer on the first etch stop layer; forming a second etch stop layer on the first electrode-material layer, the second etch stop layer being formed in such a way that it has a second pattern of through-cutouts differing from the first pattern; forming a second electrode-material layer on the second etch stop layer; forming a patterned mask on the second electrode-material layer; and carrying out a first etching step in a first direction and a second etching step in a second direction counter to the first direction in order to etch at least one first electrode unit out of the first electrode-material layer and to etch at least one second electrode unit out of the second electrode-material layer. Also described are micromechanical components.

    Abstract translation: 描述了一种用于制造微机械部件的方法，包括以下步骤：在基底基板上形成第一蚀刻停止层，第一蚀刻停止层以这样的方式形成：其具有第一图形的通孔; 在所述第一蚀刻停止层上形成第一电极材料层; 在所述第一电极材料层上形成第二蚀刻停止层，所述第二蚀刻停止层以这样的方式形成：其具有不同于所述第一图案的通孔的第二图案; 在所述第二蚀刻停止层上形成第二电极材料层; 在所述第二电极材料层上形成图案化掩模; 并且在与第一方向相反的第二方向上沿第一方向和第二蚀刻步骤进行第一蚀刻步骤，以便从第一电极材料层中蚀刻至少一个第一电极单元并蚀刻至少一个第二 电极单元排出第二电极材料层。 还描述了微机械部件。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    152.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140070336A1

    公开(公告)日：2014-03-13

    申请号：US13963409

    申请日：2013-08-09

    Applicant: DONGBU HITEK CO., LTD.

    Inventor： Chung Kyung JUNG ,  Ki Jun Yun ,  Oh Jin Jung ,  Sang Wook Ryu ,  Seong Hun Jeong ,  Sung Wook Joo

    IPC: B81C1/00 ,  B81B3/00

    CPC classification number: B81C1/00015 ,  B81B3/0018 ,  B81B2201/018 ,  B81C1/00801 ,  B81C2201/014

    Abstract: Method for manufacturing a semiconductor device includes the steps of forming a lower electrode pattern on a substrate, forming a first interlayer insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first interlayer insulating layer, forming a second interlayer insulating layer on the upper electrode pattern, forming an etch blocking layer on a side of the upper electrode pattern, wherein the etch blocking layer passes through the first interlayer insulating layer, forming a cavity which exposes the side of the etch blocking layer by etching the second interlayer insulating layer, and forming a contact ball in the cavity.

    Abstract translation: 制造半导体器件的方法包括以下步骤：在衬底上形成下电极图案，在下电极图案上形成第一层间绝缘层，在第一层间绝缘层上形成上电极图案，在第一层间绝缘层上形成第二层间绝缘层 所述上电极图案在所述上电极图案的一侧上形成蚀刻阻挡层，其中所述蚀刻阻挡层穿过所述第一层间绝缘层，形成通过蚀刻所述第二层间绝缘体而暴露所述蚀刻阻挡层侧的空腔 并且在空腔中形成接触球。

    Chip package and fabrication method thereof
    153.
    发明授权
    Chip package and fabrication method thereof 有权
    芯片封装及其制造方法

    公开(公告)号：US08637970B2

    公开(公告)日：2014-01-28

    申请号：US12855447

    申请日：2010-08-12

    Applicant: Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

    Inventor： Chia-Lun Tsai ,  Chia-Ming Cheng ,  Long-Sheng Yeou

    IPC: H01L21/301 ,  H01L21/302

    CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

    Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

    MICROELECTRONIC COMPONENT
    154.
    发明申请
    MICROELECTRONIC COMPONENT 审中-公开
    微电子元件

    公开(公告)号：US20130026659A1

    公开(公告)日：2013-01-31

    申请号：US13639370

    申请日：2011-03-22

    Applicant: Mehmet Kaynak ,  Bernd Tillack ,  Rene Scholz

    Inventor： Mehmet Kaynak ,  Bernd Tillack ,  Rene Scholz

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: B81C1/00587 ,  B81B2207/015 ,  B81B2207/07 ,  B81C2201/014

    Abstract: A method for producing a MEMS component including the steps of simultaneously embedding structure elements during producing the multi-level conductive path layer stack which structure elements are to be subsequently exposed, subsequently producing a recess that extends from a substrate backside to the multi-level conductive path layer stack, exposing the micromechanical structure elements in the multi-level conductive path layer stack through the recess. In order to increase process precision a reference mask for defining a lateral position or a lateral extension of the micromechanical structure elements to be exposed is produced, wherein the reference mask is either arranged on the substrate front side between the substrate and the multi-level conductive path layer stack or in a layer of the multi-level conductive path layer stack which layer is more proximal to the substrate than the structure element to be exposed.

    Abstract translation: 一种用于制造MEMS部件的方法，包括以下步骤：在制造多级导电路径层堆叠期间同时嵌入结构元件，该结构元件随后将被暴露，随后产生从背衬延伸到多层导电 路径层堆叠，通过凹槽暴露多层导电路径层堆叠中的微机械结构元件。 为了提高加工精度，产生用于限定要暴露的微机械结构元件的横向位置或横向延伸的参考掩模，其中参考掩模或者被布置在基板和多层导电 路径层堆叠或者在多层导电路径层堆叠的层中，该层比要暴露的结构元件更靠近衬底。

    Etching method and system
    155.
    发明授权
    Etching method and system 有权
    蚀刻方法和系统

    公开(公告)号：US08153926B2

    公开(公告)日：2012-04-10

    申请号：US12750877

    申请日：2010-03-31

    Applicant: Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

    Inventor： Yasuhiro Morikawa ,  Toshio Hayashi ,  Koukou Suu

    IPC: B23K10/00

    CPC classification number: H01L21/30655 ,  B81C1/00595 ,  B81C2201/014 ,  H01J37/3255 ,  H01J2237/334

    Abstract: An etching method and an etching system are adapted to produce a high etch selectivity for a mask, an excellent anisotropic profile and a large etching depth. An etching system according to the invention comprises a floating electrode arranged vis-à-vis a substrate electrode in a vacuum chamber and held in a floating state in terms of electric potential, a material arranged at the side of the floating electrode facing the substrate electrode to form an anti-etching film and a control unit for intermittently applying high frequency power to the floating electrode. An etching method according to the invention uses a material arranged at the side of the floating electrode opposite to the substrate electrode to form an anti-etching film as target and only rare gas as main gas and is adapted to repeat a step of forming a film on the substrate by sputtering by applying high frequency power to the floating electrode and a step of subsequently etching the substrate by suspending the application of high frequency power to the floating electrode and introducing etching gas into the vacuum chamber in a predetermined sequence.

    Abstract translation: 蚀刻方法和蚀刻系统适于产生掩模的高蚀刻选择性，优异的各向异性轮廓和大的蚀刻深度。 根据本发明的蚀刻系统包括相对于真空室中的基板电极布置并且在电位方面保持为浮置状态的浮动电极，布置在浮置电极的面向基板电极的一侧的材料 形成抗蚀刻膜和用于间歇地向浮动电极施加高频电力的控制单元。 根据本发明的蚀刻方法使用布置在与基板电极相对的浮动电极侧的材料以形成作为目标的抗蚀刻膜，并且仅将稀有气体作为主要气体，并且适于重复形成膜的步骤 通过向浮动电极施加高频电力而通过溅射在衬底上，以及通过将高频电力施加到浮动电极并以预定顺序将蚀刻气体引入真空室中而随后蚀刻衬底的步骤。

    Method of fabricating an electromechanical device including at least one active element
    157.
    发明授权
    Method of fabricating an electromechanical device including at least one active element 有权
    制造包括至少一个有源元件的机电装置的方法

    公开(公告)号：US08076169B2

    公开(公告)日：2011-12-13

    申请号：US12488882

    申请日：2009-06-22

    Applicant: Francois Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

    Inventor： Francois Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

    IPC: H01L21/00

    CPC classification number: B81C1/00238 ,  B81B2201/0271 ,  B81C1/00357 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/0191

    Abstract: The invention relates to a method of fabricating an electromechanical device including an active element, wherein the method comprises the following steps:a) making a monocrystalline first stop layer on a monocrystalline layer of a first substrate;b) growing a monocrystalline mechanical layer epitaxially on said first stop layer out of at least one material that is different from that of the stop layer;c) making a sacrificial layer on said active layer out of a material that is suitable for being etched selectively relative to said mechanical layer;d) making a bonding layer on the sacrificial layer;e) bonding a second substrate on the bonding layer; andf) eliminating the first substrate and the stop layer to reveal the surface of the mechanical layer opposite from the sacrificial layer, the active element being made by at least a portion of the mechanical layer.

    Abstract translation: 本发明涉及一种制造包括有源元件的机电装置的方法，其中该方法包括以下步骤：a）在第一衬底的单晶层上制备单晶第一阻挡层; b）在所述第一停止层上外延生长至少一种不同于所述停止层的材料的单晶机械层; c）在适合于相对于所述机械层选择性蚀刻的材料中在所述有源层上制造牺牲层; d）在牺牲层上形成结合层; e）在接合层上粘合第二衬底; 以及f）消除所述第一衬底和所述阻挡层以露出与所述牺牲层相对的所述机械层的表面，所述有源元件由所述机械层的至少一部分制成。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    158.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20110127666A1

    公开(公告)日：2011-06-02

    申请号：US12855447

    申请日：2010-08-12

    Applicant: Chia-Lun TSAI ,  Chia-Ming CHENG ,  Long-Sheng YEOU

    Inventor： Chia-Lun TSAI ,  Chia-Ming CHENG ,  Long-Sheng YEOU

    IPC: H01L23/48 ,  H01L21/50

    CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

    Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

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