公开(公告)号：US07234089B2

公开(公告)日：2007-06-19

申请号：US10011257

申请日：2001-10-27

Applicant: Gary Morton

Inventor： Gary Morton

IPC: G01R31/28

CPC classification number: G01R31/31853

Abstract: Circuitry for testing and implementing a distributed tristate bus, the circuitry being configured in the testing mode, when a first signal is supplied to a first enable input and a test enable signal is operative, the cascade circuitry outputs a cascade out signal to the cascade input via the cascade output, causing the second cascade circuitry to disable the enable input of the second tristate cell, thereby to reduce the possibility of contention of the data bus during scan testing.

Abstract translation: 用于测试和实现分布式三态总线的电路，所述电路在测试模式中配置，当第一信号被提供给第一使能输入并且测试使能信号有效时，级联电路将级联输出信号输出到级联输入 通过级联输出使得第二级联电路禁用第二三态单元的使能输入，从而减少在扫描测试期间数据总线争用的可能性。

公开(公告)号：US20070103997A1

公开(公告)日：2007-05-10

申请号：US11465535

申请日：2006-08-18

Applicant: Peter Bennett ,  Andrew Dellow

Inventor： Peter Bennett ,  Andrew Dellow

IPC: G11C7/00

CPC classification number: H04N21/443 ,  H04H60/23 ,  H04H60/80

Abstract: A filter is arranged to selectively block or allow a data access command from an initiator according to whether the initiator is secure or insecure and whether a data source or destination being accessed is privileged or unprivileged. The data access command contains an identification of the initiator from which the data access command originated and an identification of the data source or destination being accessed. The security filter compares the initiator identification and data source or destination identification contained within the data access command with a list of those initiators defined as secure and a list of those data sources or destinations which are defined as unprivileged. The filter then blocks or allows the data access command signal according to a set of rules.

Abstract translation: 布置过滤器以根据启动器是安全的还是不安全的以及被访问的数据源或目的地是特权还是非特权来选择性地阻止或允许来自发起者的数据访问命令。 数据访问命令包含发起数据访问命令的启动器的标识以及所访问的数据源或目的地的标识。 安全过滤器将包含在数据访问命令中的启动器标识和数据源或目的地标识与定义为安全的那些启动器的列表以及被定义为无特权的那些数据源或目的地的列表进行比较。 然后，滤波器根据一组规则阻止或允许数据访问命令信号。

公开(公告)号：US20070024316A1

公开(公告)日：2007-02-01

申请号：US11461239

申请日：2006-07-31

Applicant: Andrew Dellow

Inventor： Andrew Dellow

IPC: H03K19/00

CPC classification number: G06F21/70 ,  G06F21/73

Abstract: A method distributes personalized circuits to one or more parties. The method distributes a generic circuit to each party, encrypts a unique personalization value using a secret encryption key, and transmits each encrypted personalization value to the corresponding party. Each party then stores the encrypted personalization value in their circuit. The stored encrypted personalization value allows a piece of software to be properly executed by the circuit. A semiconductor integrated circuit is arranged to execute a piece of software that inputs a personalization value as an input parameter. The circuit comprises a personalization memory arranged to store an encrypted personalization value; a key memory for storing a decryption key; a control unit comprising a cryptographic circuit arranged to decrypt the encrypted personalization value using the decryption key; and a processor arranged to receive the decrypted personalization value and execute the software using the decrypted personalization value.

Abstract translation: 一种方法将个性化电路分配给一个或多个方。 该方法将通用电路分配给每一方，使用秘密加密密钥加密唯一的个性化值，并将每个加密的个性化值发送给相应方。 各方然后将加密的个性化值存储在其电路中。 存储的加密个性化值允许一个软件被电路正确地执行。 半导体集成电路被布置为执行输入个性化值作为输入参数的软件。 该电路包括个人化存储器，其被布置成存储加密的个性化值; 用于存储解密密钥的密钥存储器; 控制单元，包括密码电路，其被设置为使用所述解密密钥对所述加密的个性化值进行解密; 以及被配置为接收解密的个性化值并使用解密的个性化值来执行软件的处理器。

公开(公告)号：US07171599B2

公开(公告)日：2007-01-30

申请号：US10406058

申请日：2003-04-02

Applicant: Deepak Agarwal

Inventor： Deepak Agarwal

IPC: B01R31/28 ,  G06F7/02

CPC classification number: G01R31/318519 ,  G01R31/318516 ,  H03K19/17764

Abstract: A field programmable device is disclosed, including a plurality of logic blocks; a plurality of connections connecting the logic blocks; configuration circuitry for outputting configuration data for programming the field programmable device, the configuration circuitry providing at least one pair of outputs; and error detection circuitry for comparing the outputs to determine if there has been a configuration error.

Abstract translation: 公开了一种现场可编程装置，包括多个逻辑块; 连接逻辑块的多个连接; 用于输出用于编程现场可编程设备的配置数据的配置电路，所述配置电路提供至少一对输出; 以及用于比较输出以确定是否存在配置错误的错误检测电路。

公开(公告)号：US07154344B2

公开(公告)日：2006-12-26

申请号：US11016690

申请日：2004-12-17

Applicant: William Thies ,  Chris Lawley

Inventor： William Thies ,  Chris Lawley

IPC: H03L7/10 ,  H03L7/18

CPC classification number: H03L7/095 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/197 ,  Y10S331/02

Abstract: A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.

Abstract translation: 一种锁相环（PLL）电路，包括：用于接收输出信号的反馈分频电路，所述反馈分频电路经布置以在第一操作模式中将所述输出信号除以第一分频因子，以及在第二模式中的第二除法系数 的操作。

公开(公告)号：US07057382B2

公开(公告)日：2006-06-06

申请号：US10896362

申请日：2004-07-21

Applicant: Anna Sigurdardottir

Inventor： Anna Sigurdardottir

IPC: G05F3/16 ,  G05F3/20

CPC classification number: G05F3/245

Abstract: A voltage reference circuit comprising a first reference voltage source, a second reference voltage source, at least one of said first and second reference voltage sources being dependent on temperature, and first circuitry connected to at least one of said first and second reference voltage sources to provide a third reference voltage, said third reference voltage being dependent on temperature.

Abstract translation: 一种电压参考电路，包括第一参考电压源，第二参考电压源，所述第一和第二参考电压源中的至少一个取决于温度，第一电路连接到所述第一和第二参考电压源中的至少一个， 提供第三参考电压，所述第三参考电压取决于温度。

公开(公告)号：US07039666B2

公开(公告)日：2006-05-02

申请号：US10291219

申请日：2002-11-07

Applicant: Tariq Kurd

Inventor： Tariq Kurd

IPC: G06F7/38

CPC classification number: G06F7/535 ,  G06F7/5525

Abstract: The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.

公开(公告)号：US07038494B2

公开(公告)日：2006-05-02

申请号：US10274098

申请日：2002-10-17

Applicant: Gary Morton

Inventor： Gary Morton

IPC: H03K19/00

CPC classification number: G01R31/318541 ,  G01R31/318544 ,  G01R31/318594

Abstract: A scan chain element in an integrated circuit, the scan chain element including; a first latch connected to accept test data as an input, a second latch connected to accept the output of the first latch as an input, control logic for accepting a clock signal and a hold signal, the scan chain element being operable in a first mode such that the control logic is configured to supply the clock signal to the first latch and subsequently, in response to the hold signal, to supply the clock signal to the second latch to latch the data from the output of the first latch.

Abstract translation: 一种集成电路中的扫描链元件，所述扫描链元件包括： 第一锁存器，其被连接以接受作为输入的测试数据;第二锁存器，被连接以接受第一锁存器的输出作为输入，用于接受时钟信号和保持信号的控制逻辑，扫描链元件可以第一模式操作 使得控制逻辑被配置为将时钟信号提供给第一锁存器，随后响应于保持信号，将时钟信号提供给第二锁存器，以从第一锁存器的输出锁存数据。

公开(公告)号：US20050276264A1

公开(公告)日：2005-12-15

申请号：US11144396

申请日：2005-06-03

Applicant: Rodrigo Cordero ,  Paul Cox ,  Andrew Dellow

Inventor： Rodrigo Cordero ,  Paul Cox ,  Andrew Dellow

IPC: H04L12/28 ,  H04N5/00 ,  H04N7/52

CPC classification number: H04N21/64322 ,  H04N21/4381 ,  H04N21/4622

Abstract: A system including input circuitry for receiving from one of a plurality of sources at least one packet stream including a plurality of packets for providing audio, video, private data and/or associated information; at least one output for outputting at least one packet of the at least one packet stream to circuitry arranged to provide an output stream; wherein the system is arranged to provide a tag indicative of the source, the tag being associated with the at least one packet.

Abstract translation: 一种包括用于从多个源中的一个源接收包括用于提供音频，视频，私人数据和/或相关信息的多个分组的至少一个分组流的输入电路的系统; 至少一个输出，用于将至少一个分组流的至少一个分组输出到布置成提供输出流的电路; 其中所述系统被布置为提供指示所述源的标签，所述标签与所述至少一个分组相关联。

公开(公告)号：US20050269607A1

公开(公告)日：2005-12-08

申请号：US11144112

申请日：2005-06-03

Applicant: Robert Henderson

Inventor： Robert Henderson

IPC: H01L31/062 ,  H04N5/374 ,  H04N5/3745

CPC classification number: H04N5/37457 ,  H04N5/3741

Abstract: The image sensor includes an array of pixels. Each pixel has a pinned photodiode which transfers charge via a transfer gate to a floating diffusion, from which output is provided by a source follower. Each column has a voltage supply line and a signal line. Each row has a transfer gate control line, a read/reset control line, and a read/reset voltage line which receives alternately zero volts and a predetermined positive voltage from a decoder circuit.

Abstract translation: 图像传感器包括像素阵列。 每个像素具有钉扎光电二极管，其通过传输栅极将电荷传输到浮动扩散，从源极跟随器输出该输出。 每列具有电源线和信号线。 每行具有传输门控制线，读/复位控制线和从解码器电路交替接收零伏特和预定正电压的读/复电压线。