公开(公告)号：USD864275S1

公开(公告)日：2019-10-22

申请号：US29639484

申请日：2018-03-06

Applicant: VIA TECHNOLOGIES, INC.

Designer： Chih-Wei Huang

公开(公告)号：US10417144B2

公开(公告)日：2019-09-17

申请号：US15631154

申请日：2017-06-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Tze-Shiang Wang

IPC: G06F13/10 ,  G06F13/40 ,  G11B33/12

Abstract: A bridge device including a first connector, a first transceiver, a second connector, a second transceiver, a voltage processor, and a controller is provided. The first connector is configured to couple to a host and includes a first pin. The first transceiver is coupled between the first pin and a node and includes a first current limiter. The second connector is configured to couple to a peripheral device and includes a second pin. The second transceiver is coupled between the node and the second pin and includes a second current limiter. The voltage processor processes the voltage of the node to generate an operation voltage. The controller receives the operation voltage to determine whether to turn on at least one of the first and second transceivers.

公开(公告)号：US20190205245A1

公开(公告)日：2019-07-04

申请号：US16007025

申请日：2018-06-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Zhongyi GAO ,  Xiaoyu YANG

IPC: G06F12/02 ,  G11C16/16 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7211 ,  G11C16/16 ,  G11C16/349

Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. A minimal erase number of blocks have a minimal erase count in the plurality of blocks. When one of the minimal erase number of blocks is erased, the controller subtracts 1 from the minimal erase number.

公开(公告)号：US10303536B2

公开(公告)日：2019-05-28

申请号：US15265909

申请日：2016-09-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F11/00 ,  G06F11/07 ,  G06F3/06 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A non-volatile memory device including a non-volatile memory and a controller is provided. The non-volatile memory includes a plurality of closed blocks and a plurality of open blocks. The controller derives a ratio value according to the write workload of the non-volatile memory between a first time point and a second time point and then performs a patrol read on a portion of the closed blocks according to the ratio value.

公开(公告)号：USD849107S1

公开(公告)日：2019-05-21

申请号：US29617354

申请日：2017-09-13

Applicant: VIA TECHNOLOGIES, INC.

Designer： Chih-Wei Huang

公开(公告)号：US20190114317A1

公开(公告)日：2019-04-18

申请号：US15867747

申请日：2018-01-11

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang ,  Jing-Jing Guo

IPC: G06F17/27

Abstract: A natural language recognizing apparatus including an input device, a processing device and a storage device is provided. The input device is configured to provide a natural language data. The storage device is configured to store a plurality of program modules. The program modules include a grammar analysis module. The processing device executes the grammar analysis module to analyze the natural language data through a formal grammar model, and generate a plurality of string data. When at least one of the string data conforms to a preset grammar condition, the processing device judges the at least one of the string data is an intention data, and the processing device outputs a corresponding response signal according to the intention data. In addition, a natural language recognizing method is also provided.

公开(公告)号：US10223017B2

公开(公告)日：2019-03-05

申请号：US15193126

申请日：2016-06-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3206

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.

公开(公告)号：US10211813B2

公开(公告)日：2019-02-19

申请号：US14976363

申请日：2015-12-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Cheng-Chun Yeh

IPC: G06F13/40 ,  H03H11/28

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

公开(公告)号：US10133700B2

公开(公告)日：2018-11-20

申请号：US15389517

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12 ,  G11C8/18 ,  G11C7/10

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time. The bit lag control element has delay lock control that is configured to select one of a plurality of successively delayed versions of the lag pulse signal that coincides with the assertion the replicated strobe signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions comprises inputs to the mux, and where the plurality of successively delayed versions comprises outputs a first plurality of series-coupled matched inverter pairs. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the time.

公开(公告)号：US20180314483A1

公开(公告)日：2018-11-01

申请号：US15654666

申请日：2017-07-19

Applicant: VIA Technologies, Inc.

Inventor： Steve Shu Liu

IPC: G06F3/14 ,  H04N21/41 ,  H04N5/268 ,  G09G3/34

Abstract: A system, a control apparatus and a control method for distributed video display are provided. The system includes an image source device configured to provide image data, a plurality of displays, a plurality of display chips respectively coupled to the displays and connected with the video source device through a network, and a control apparatus connected with the image source device and the display chips through the network and configured to transmit a playback signal to each of the display chips to control the display chips to receive the image data from the image source device and convert the received image data into display frames capable of being played by the displays. The control apparatus further transmits a synchronizing signal to each display chip to control the display chips to synchronize the clocks with each other according to the synchronizing signal and sets each of the display chips with a fixed delay time after receiving the image data to synchronously play the display frames on the displays.