公开(公告)号：US11742429B2

公开(公告)日：2023-08-29

申请号：US17508843

申请日：2021-10-22

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Li Huey Tan ,  Tristan A. Tronic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78681 ,  H01L29/0669 ,  H01L29/20 ,  H01L29/42384 ,  H01L29/66742

Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.

公开(公告)号：US11721735B2

公开(公告)日：2023-08-08

申请号：US17580550

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Van H. Le ,  Abhishek A. Sharma ,  Tahir Ghani ,  Willy Rachmady ,  Rishabh Mehandru ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Shriram Shivaraman

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/66545

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US11522060B2

公开(公告)日：2022-12-06

申请号：US16142036

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Justin Weber ,  Matthew Metz ,  Arnab Sen Gupta ,  Abhishek Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Charles Kuo ,  Nazila Haratipour ,  Shriram Shivaraman ,  Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Sean Ma

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  H01L27/108 ,  H01L21/02 ,  H01L29/267 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11515420B2

公开(公告)日：2022-11-29

申请号：US16643927

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Dax M. Crum ,  Cory E. Weber ,  Rishabh Mehandru ,  Harold Kennel ,  Benjamin Chu-Kung

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/417 ,  H01L29/08 ,  H01L29/165 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L29/267

Abstract: An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.

公开(公告)号：US11450750B2

公开(公告)日：2022-09-20

申请号：US16146654

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Van H. Le ,  Shriram Shivaraman ,  Abhishek Sharma

IPC: H01L23/532 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/10 ,  H01L27/105

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT). The transistor includes a source electrode oriented in a horizontal direction, and a channel layer in contact with a portion of the source electrode and oriented in a vertical direction substantially orthogonal to the horizontal direction. A gate dielectric layer conformingly covers a top surface of the source electrode and surfaces of the channel layer. A gate electrode conformingly covers a portion of the gate dielectric layer. A drain electrode is above the channel layer, oriented in the horizontal direction. A current path is to include a current portion from the source electrode along a gated region of the channel layer under the gate electrode in the vertical direction, and a current portion along an ungated region of the channel layer in the horizontal direction from the gate electrode to the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US11450527B2

公开(公告)日：2022-09-20

申请号：US16303125

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Marc C. French ,  Seung Hoon Sung ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Ashish Agrawal

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

公开(公告)号：US11444204B2

公开(公告)日：2022-09-13

申请号：US15939081

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Sean T. Ma ,  Jack Kavalieros ,  Benjamin Chu-Kung

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.

公开(公告)号：US20220278227A1

公开(公告)日：2022-09-01

申请号：US17745822

申请日：2022-05-16

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US11222977B2

公开(公告)日：2022-01-11

申请号：US16641022

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US11195924B2

公开(公告)日：2021-12-07

申请号：US16094151

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L21/285 ,  H01L21/768 ,  H01L29/78

Abstract: An interlayer film is deposited on a device layer on a substrate. A contact layer is deposited on the interlayer film. The interlayer film has a broken bandgap alignment to the device layer to reduce a contact resistance of the contact layer to the device layer.