公开(公告)号：US20220059702A1

公开(公告)日：2022-02-24

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US12107170B2

公开(公告)日：2024-10-01

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/7869

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US11171239B2

公开(公告)日：2021-11-09

申请号：US16570965

申请日：2019-09-13

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US20210083122A1

公开(公告)日：2021-03-18

申请号：US16570965

申请日：2019-09-13

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US11843058B2

公开(公告)日：2023-12-12

申请号：US17516569

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11462568B2

公开(公告)日：2022-10-04

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Justin Weber ,  Harold Kennel ,  Willy Rachmady ,  Gilbert Dewey ,  Van H. Le ,  Abhishek Sharma ,  Patrick Morrow ,  Ashish Agrawal

IPC: H01L27/12 ,  H01L21/8256 ,  H01L29/78 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105854A1

公开(公告)日：2024-03-28

申请号：US18528545

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11522060B2

公开(公告)日：2022-12-06

申请号：US16142036

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Justin Weber ,  Matthew Metz ,  Arnab Sen Gupta ,  Abhishek Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Charles Kuo ,  Nazila Haratipour ,  Shriram Shivaraman ,  Van H. Le ,  Tahir Ghani ,  Jack T. Kavalieros ,  Sean Ma

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/205 ,  H01L29/49 ,  H01L29/786 ,  H01L29/45 ,  H01L27/108 ,  H01L21/02 ,  H01L29/267 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11171243B2

公开(公告)日：2021-11-09

申请号：US16455581

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L29/221 ,  H01L21/8238 ,  H01L27/092

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11637185B2

公开(公告)日：2023-04-25

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin Weber ,  Harold Kennel ,  Abhishek Sharma ,  Christopher Jezewski ,  Matthew V. Metz ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Van H. Le ,  Arnab Sen Gupta

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L21/322 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L29/267

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.