公开(公告)号：US11469766B2

公开(公告)日：2022-10-11

申请号：US16024052

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Charles Kuo ,  Willy Rachmady

IPC: H03M1/66 ,  H03M1/00 ,  H03M1/74

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

公开(公告)号：US11430943B2

公开(公告)日：2022-08-30

申请号：US16022561

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30 ,  H01L27/22 ,  H01L43/10

Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.

公开(公告)号：US20200005861A1

公开(公告)日：2020-01-02

申请号：US16022547

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Brian Doyle ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster comprises a magnetic material layer. The booster may further comprise an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

公开(公告)号：US20190304653A1

公开(公告)日：2019-10-03

申请号：US15942434

申请日：2018-03-31

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Charles Kuo ,  Mark Doczy ,  Kevin O'Brien

IPC: H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir—Mn SOT material and the free magnet have an in-plane magnetic exchange bias.

公开(公告)号：US20190189913A1

公开(公告)日：2019-06-20

申请号：US16329169

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Kaan Oguz ,  Satyarth Suri ,  Kevin O'Brien ,  Mark Doczy ,  Charles Kuo

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/16 ,  G11C11/161 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.

公开(公告)号：US11386951B2

公开(公告)日：2022-07-12

申请号：US16022547

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Brian Doyle ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

公开(公告)号：US20190385657A1

公开(公告)日：2019-12-19

申请号：US16012634

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Charles Kuo ,  Benjamin Chu-kung ,  Muhammad Khellah

IPC: G11C11/38 ,  G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: An apparatus is provided which comprises: a storage node; a first device coupled to the storage node; a second device coupled to a first reference and the storage node, wherein the second device has negative differential resistance (NDR); a third device coupled to a second reference and the storage node, wherein the third device has NDR; and a circuitry for reading data, the circuitry coupled to the storage node and the first, second, and third devices, wherein the first, second, and third devices, and the circuitry are positioned in a backend-of-line (BEOL) of a die.

公开(公告)号：US12058847B2

公开(公告)日：2024-08-06

申请号：US16888910

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek A. Sharma ,  Charles Kuo ,  Brian S. Doyle ,  Urusa Shahriar Alaan ,  Van H Le ,  Elijah V. Karpov ,  Kaan Oguz ,  Arnab Sen Gupta

IPC: H10B12/00 ,  H01L25/065

CPC classification number: H10B12/30 ,  H01L25/0657

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

公开(公告)号：US20230147275A1

公开(公告)日：2023-05-11

申请号：US17524075

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Charles Kuo ,  Kaan Oguz

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L45/10 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16

Abstract: A memory device including a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell of the plurality of memory cells comprises a conductive ferroelectric material and wherein the conductive ferroelectric material is in series with a dielectric material.

公开(公告)号：US11348970B2

公开(公告)日：2022-05-31

申请号：US15960218

申请日：2018-04-23

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Benjamin Buford ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/04 ,  H01L45/00 ,  B82Y25/00

Abstract: A spin orbit torque (SOT) memory device includes an SOT electrode on an upper end of an MTJ device. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet and is coupled with a conductive interconnect at a lower end of the MTJ device. The SOT electrode has a footprint that is substantially the same as a footprint of the MTJ device. The SOT device includes a first contact and a second contact on an upper surface of the SOT electrode. The first contact and the second contact are laterally spaced apart by a distance that is no greater than a length of the MTJ device.