公开(公告)号：US06611029B1

公开(公告)日：2003-08-26

申请号：US10290158

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.

Abstract translation: 半导体器件可以包括基板和形成在该副墨滴上的绝缘层。 鳍可以形成在绝缘层上，并且可以包括多个侧表面和顶表面。 第一栅极可以形成在靠近鳍片的多个侧表面中的一个的绝缘层上。 第二栅极，并且可以形成在与第一栅极分离并且靠近鳍片的多个侧表面中的另一个的绝缘层上。

公开(公告)号：US06531368B1

公开(公告)日：2003-03-11

申请号：US09825750

申请日：2001-04-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/268 ,  H01L21/2807 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66583

Abstract: A method of fabricating a semiconductor device, having a locally-formed metal oxide high-k gate insulator, involving: nitriding a substrate to form a thin silicon nitride layer; depositing a thin metal film on the thin silicon nitride layer; forming a localized metal oxide layer from the thin metal film, wherein the a thick nitride layer is deposited on the thin metal film, the thick nitride layer is patterned, the at least one exposed thin metal film portion is locally oxidized, by heating, wherein the oxidizing is performed by local laser irradiation; forming a gate stack having the localized metal oxide layer and a gate electrode, wherein the a thick gate material is deposited in the electrode cavity and on the localized metal oxide layer; the thick gate material is polished, thereby forming the gate electrode; and the thick nitride layer along with the at least one covered thin metal film portion are removed, thereby forming the gate stack; and completing fabrication of the device, and a device thereby formed.

Abstract translation: 一种制造具有局部形成的金属氧化物高k栅极绝缘体的半导体器件的方法，包括：氮化氮化硅层，形成薄的氮化硅层; 在薄氮化硅层上沉积薄金属薄膜; 从所述薄金属膜形成局部金属氧化物层，其中所述厚氮化物层沉积在所述薄金属膜上，所述厚氮化物层被图案化，所述至少一个暴露的金属薄膜部分通过加热而局部氧化，其中 通过局部激光照射进行氧化; 形成具有局部金属氧化物层和栅电极的栅极堆叠，其中厚栅极材料沉积在电极腔和局部金属氧化物层上; 对厚栅极材料进行抛光，从而形成栅电极; 并且去除厚氮化物层与至少一个覆盖的薄金属膜部分，从而形成栅极堆叠; 并完成该装置的制造以及由此形成的装置。

公开(公告)号：US06524920B1

公开(公告)日：2003-02-25

申请号：US09779988

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/517 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The gate structure includes L-shaped liners. The semiconductor material can be silicided. A shallow source drain implant can also be provided.

Abstract translation: 集成电路的制造方法利用固相外延形成升高的源极区域和升高的漏极区域。 该方法包括提供非晶半导体材料并使非晶半导体材料结晶而不损坏高k栅介质层。 门结构包括L形衬垫。 半导体材料可以被硅化。 还可以提供浅源极漏极植入物。

公开(公告)号：US06507078B1

公开(公告)日：2003-01-14

申请号：US10131858

申请日：2002-04-25

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

Abstract: A MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon structure disposed on a gate dielectric over the channel region. A drain silicide and a source silicide having a first silicide thickness are formed in the drain region and the source region, respectively. A dielectric layer is deposited over the drain region, the source region, and the gate. The dielectric layer is polished until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. The capping layer on the polysilicon structure of the gate is etched away such that the top of the polysilicon structure is exposed. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon structure are exposed. A polysilicon spacer is formed at the exposed sidewalls at the top portion of the polysilicon structure. A silicidation metal is deposited on the top of the polysilicon structure that is exposed and on the polysilicon spacer. A silicidation anneal is performed with the silicidation metal and the polysilicon structure that is exposed and the polysilicon spacer to form a gate silicide having a second silicide thickness on top of the polysilicon structure of the gate. Because the gate silicide is formed with the added polysilicon spacer at the exposed sidewalls of the polysilicon structure, the gate silicide has a width that is larger than a width of the polysilicon structure of the gate. In addition, the gate silicide is formed in a separate step from the step for forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide.

公开(公告)号：US06492670B1

公开(公告)日：2002-12-10

申请号：US09821258

申请日：2001-03-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2980

CPC classification number: H01L29/66492 ,  H01L29/665

Abstract: A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有局部密封深口袋区域的集成电路的方法利用虚拟或牺牲栅极间隔物。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成袋区域。 在硅化后提供掺杂剂。 开口可以填充间隔件。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06475869B1

公开(公告)日：2002-11-05

申请号：US09793055

申请日：2001-02-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78687

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.

Abstract translation: 一种制造具有含有锗的沟道区的集成电路的方法。 该方法可以提供双平面栅极结构。 栅极结构可以设置在沟道区域的侧壁上。 含锗的半导体材料可以增加与晶体管相关的电荷迁移率。 外延工艺可以形成通道区域。 可以使用绝缘体上硅。

公开(公告)号：US06465312B1

公开(公告)日：2002-10-15

申请号：US09845602

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665

Abstract: A method of fabricating CMOS transistors having an elevated source-drain structure. The method utilizes the formation of L-shaped spacers on the gate stack followed by amorphous silicon (a-Si) deposition. By way of example, the L-shaped spacers are formed by depositing a first and second spacer layer over the gate stack. The second spacer layer is etched to create a dummy spacer adjacent the gate stack. The regions of the first spacer which are unprotected by the dummy spacer are etched away. The dummy spacer is removed wherein L-shaped spacers of the first spacer layer remain adjacent the gate stack. Deep source-drain implantation is performed on the deposited layer of silicon. After implantation, silicide may be formed on the amorphous silicon at a gate-to-contact spacing determined by the thickness of the L-shaped spacer.

Abstract translation: 一种制造具有升高的源极 - 漏极结构的CMOS晶体管的方法。 该方法利用在栅极堆叠上形成L形间隔物，随后是非晶硅（a-Si）沉积。 作为示例，通过在栅极堆叠上沉积第一和第二间隔层来形成L形间隔物。 蚀刻第二间隔层以产生邻近栅叠层的虚拟间隔物。 被虚拟间隔物保护的第一间隔物的区域被蚀刻掉。 去除虚拟间隔物，其中第一间隔层的L形间隔物保持邻近栅极堆叠。 在硅的沉积层上进行深源极 - 漏极注入。 在注入之后，硅化物可以以由L形间隔物的厚度确定的栅极 - 接触间距在非晶硅上形成。

公开(公告)号：US06448165B1

公开(公告)日：2002-09-10

申请号：US09746397

申请日：2000-12-21

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L21/32134 ,  Y10S977/707 ,  Y10S977/888 ,  Y10S977/891 ,  Y10S977/892

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate electrode material is deposited on the layer of gate dielectric material, and the gate electrode material is a semiconductor material. At least one of an N-type dopant or a P-type dopant or a neutral dopant is implanted into the layer of gate electrode material such that the at least one of an N-type dopant or a P-type dopant or a neutral dopant has a dopant concentration in the layer of gate electrode material. A layer of photo-resist material, a layer of BARC (bottom anti-reflective coating) material, and the layer of gate electrode material are patterned to form a gate structure of the field effect transistor. The gate structure is comprised of the remaining gate electrode material, and the BARC (bottom anti-reflective coating) material remains on the gate structure. The BARC (bottom anti-reflective coating) material is then stripped from the gate structure using an etching reactant that etches both of the BARC (bottom anti-reflective coating) material and the gate electrode material. An etch rate of the gate electrode material in the etching reactant increases with an increase of the dopant concentration of the at least one of an N-type dopant or a P-type dopant or a neutral dopant within the gate electrode material. Sidewalls of the gate structure are trimmed by a trim length during the step of stripping the BARC (bottom anti-reflective coating) material from the gate structure. Thus, the dopant concentration of the at least one of an N-type dopant or a P-type dopant or a neutral dopant in the gate electrode material is adjusted to control the trim length of the gate structure.

Abstract translation: 为了在半导体衬底的有源器件区域内制造场效应晶体管，在半导体衬底上沉积一层栅介质材料。 栅极材料层沉积在栅极介电材料层上，栅电极材料是半导体材料。 N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种注入到栅电极材料层中，使得N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种 在栅极材料层中具有掺杂剂浓度。 将一层光致抗蚀剂材料，一层BARC（底部抗反射涂层）材料和该栅极电极材料层图案化以形成该场效应晶体管的栅极结构。 栅极结构由剩余的栅电极材料组成，并且BARC（底部抗反射涂层）材料保留在栅极结构上。 然后使用蚀刻BARC（底部抗反射涂层）材料和栅电极材料的蚀刻反应物，从栅极结构剥离BARC（底部抗反射涂层）材料。 蚀刻反应物中的栅电极材料的蚀刻速率随着栅极电极材料中的N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种的掺杂剂浓度的增加而增加。 在从栅极结构剥离BARC（底部抗反射涂层）材料的步骤期间，栅极结构的侧壁被修剪长度。 因此，调整栅电极材料中的N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种的掺杂剂浓度以控制栅极结构的修整长度。

公开(公告)号：US06448114B1

公开(公告)日：2002-09-10

申请号：US10128831

申请日：2002-04-23

Applicant: Judy Xilin An ,  Bin Yu ,  William G. En

Inventor： Judy Xilin An ,  Bin Yu ,  William G. En

IPC: H01L218234

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile. The method also includes forming a plurality of partially depleted semiconductor devices from the active layer in the area of a thicker of the first and the second tiles and forming a plurality of fully depleted semiconductor devices from the active layer in the area of a thinner of the first and the second tiles.

Abstract translation: 一种制造具有不均匀厚度的有源层的绝缘体上硅（SOI）芯片的方法。 该方法包括提供基板的步骤; 在衬底上提供掩埋氧化物层（BOX）; 在BOX层上提供有源层，活性层具有最初均匀的厚度; 将活性层分成至少第一和第二瓦片; 并且改变第二瓦片区域中活性层的厚度。 该方法还包括在第一和第二瓦片较厚的区域中从有源层形成多个部分耗尽的半导体器件，并且在较薄的区域中从有源层形成多个完全耗尽的半导体器件 第一和第二个瓷砖。

公开(公告)号：US06436773B1

公开(公告)日：2002-08-20

申请号：US09846842

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/4238 ,  H01L29/41758 ,  H01L29/6659

Abstract: For fabricating a test field effect transistor on a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A dummy structure is formed on the gate electrode material, and the dummy structure is disposed over a shaped area of the gate electrode material and of the semiconductor substrate. The dummy structure has at least one sidewall around a perimeter of the shaped area. A spacer structure is formed to surround the at least one sidewall of the dummy structure outside of the perimeter of the shaped area. The dummy structure is etched away such that the shaped area of the gate electrode material is exposed and such that the spacer structure remains outside of the perimeter of the shaped area. Any exposed regions of the gate electrode material and of the gate dielectric material not under the spacer structure are etched away. The gate dielectric material remaining under the spacer structure forms a gate dielectric of the test field effect transistor, and the gate electrode material remaining under the spacer structure forms a gate electrode of the test field effect transistor. A drain and source dopant is implanted into exposed regions of the semiconductor substrate to form a first drain or source junction within the shaped area surrounded by the gate dielectric and the gate electrode, and to form a second drain or source junction outside the shaped area beyond the gate dielectric and the gate electrode. A width of the test field effect transistor is the perimeter of the shaped area, and a length of the test field effect transistor is the width of the gate dielectric and the gate electrode extending out from the perimeter of the shaped area.

Abstract translation: 为了在半导体衬底上制造测试场效应晶体管，在半导体衬底上沉积一层栅极电介质材料，并且在该栅极电介质材料层上沉积一层栅电极材料。 在栅电极材料上形成虚拟结构，并且将虚设结构设置在栅电极材料和半导体衬底的成形区域上。 虚拟结构具有围绕成形区域的周边的至少一个侧壁。 形成间隔结构以围绕该成形区域周边外部的该虚拟结构的至少一个侧壁。 蚀刻掉虚拟结构，使得栅电极材料的成形区域被暴露，并且使得间隔结构保持在成形区域的周边的外侧。 栅极电极材料的任何暴露区域和不在间隔结构下方的栅极电介质材料被蚀刻掉。 保留在间隔结构之下的栅极电介质材料形成测试场效应晶体管的栅极电介质，并且保留在间隔结构之下的栅电极材料形成测试场效应晶体管的栅电极。 将漏极和源极掺杂剂注入到半导体衬底的暴露区域中，以在由栅极电介质和栅极电极包围的成形区域内形成第一漏极或源极结，并且在成形区域外部形成超出第二漏极或源极结 栅极电介质和栅电极。 测试场效应晶体管的宽度是成形区域的周长，并且测试场效应晶体管的长度是从成形区域的周边延伸出的栅极电介质和栅电极的宽度。