公开(公告)号：US20050062091A1

公开(公告)日：2005-03-24

申请号：US10964204

申请日：2004-10-12

Applicant: Yi Ding

Inventor： Yi Ding

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7887

Abstract: In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

公开(公告)号：US20050032306A1

公开(公告)日：2005-02-10

申请号：US10440466

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/3205 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A control gate layer (170) for a nonvolatile memory cell is formed over a select gate (140). The control gate layer protrudes upward over the select gate. An auxiliary layer (1710) is formed over the control gate layer so as to expose a protruding portion of the control gate layer. The protruding portion is processed (e.g. oxidized) to form a protective layer (1720) selectively on the control gate layer but not on the auxiliary layer. The auxiliary layer is then removed. Then the control gate layer is etched selectively to the protective layer. The protruding portion of the control gate layer is not etched away because it is protected by the protective layer. This portion provides a self-aligned control gate. The protective layer can then be removed, and a conductive material (2920), e.g. metal silicide, can be formed selectively on the protruding portion of the control gate layer in a self-aligned manner to reduce the control gate resistance. Other embodiments are also provided.

Abstract translation: 用于非易失性存储单元的控制栅极层（170）形成在选择栅极（140）上。 控制栅极层在选择栅极上向上突出。 辅助层（1710）形成在控制栅极层上，以暴露控制栅极层的突出部分。 突出部分被处理（例如氧化）以在控制栅极层上选择性地形成保护层（1720），但不在辅助层上。 然后除去辅助层。 然后将控制栅层选择性地蚀刻到保护层。 控制栅极层的突出部分不被蚀刻掉，因为它被保护层保护。 该部分提供自对准控制门。 然后可以去除保护层，并且导电材料（2920） 金属硅化物可以以自对准方式选择性地形成在控制栅极层的突出部分上，以减小控制栅极电阻。 还提供了其他实施例。

公开(公告)号：US20050026366A1

公开(公告)日：2005-02-03

申请号：US10632154

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory having a memory cell with two floating gates, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness.

Abstract translation: 在具有两个浮置栅极的非易失性存储单元的制造中，与选择栅极相同的层（140）形成一个或多个外围晶体管栅极。 用于这些外围晶体管的栅极电介质（130）和用于选择栅极的栅极电介质（130）同时形成。 在具有具有两个浮置栅极的存储单元的非易失性存储器中，用于外围晶体管的栅极电介质（130）和选择栅极（140）的栅极电介质（130）具有相同的厚度。

公开(公告)号：US06846712B2

公开(公告)日：2005-01-25

申请号：US10440508

申请日：2003-05-16

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529

Abstract: In a nonvolatile memory, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed simultaneously. In a nonvolatile memory, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness. Portions of the control gates (170) overlie the select gates.

Abstract translation: 在非易失性存储器中，与选择栅极相同的层（140）形成一个或多个外围晶体管栅极。 用于这些外围晶体管的栅极电介质（130）和用于选择栅极的栅极电介质（130）同时形成。 在非易失性存储器中，用于外围晶体管的栅极电介质（130）和用于选择栅极（140）的栅极电介质（130）具有相同的厚度。 控制门（170）的一部分覆盖选择门。

公开(公告)号：US06838342B1

公开(公告)日：2005-01-04

申请号：US10678317

申请日：2003-10-03

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328

Abstract: A floating gate of a nonvolatile memory cell is formed from two conductive layers (410.1, 410.2). A dielectric (210) in substrate isolation regions and the first of the two conductive layers providing the floating gates (410.1) are formed so that the dielectric has an exposed sidewall. At least the top portion of the sidewall is exposed. Then some of the dielectric is removed from the exposed portions of the dielectric sidewalls to laterally recess the sidewalls. Then the second conductive layer (410.2) for the floating gates is formed. The recessed sidewalls of the dielectric allow the second conductive layer to expand laterally, thus increasing the capacitive coupling between the floating and control gates and improving the gate coupling ratio.

Abstract translation: 非易失性存储单元的浮栅由两个导电层（410.1,410.2）形成。 形成衬底隔离区域中的电介质（210）和提供浮置栅极（410.1）的两个导电层中的第一个，使得电介质具有暴露的侧壁。 至少暴露侧壁的顶部。 然后从电介质侧壁的暴露部分去除一些电介质以横向凹入侧壁。 然后形成用于浮动栅极的第二导电层（410.2）。 介质的凹陷侧壁允许第二导电层横向膨胀，从而增加浮动栅极和控制栅极之间的电容耦合并提高栅极耦合比。

公开(公告)号：US06580977B2

公开(公告)日：2003-06-17

申请号：US09761285

申请日：2001-01-16

Applicant: Yi Ding ,  Joseph Carl Burba

Inventor： Yi Ding ,  Joseph Carl Burba

IPC: B60K900

CPC classification number: B60L11/1894 ,  B60L11/1887 ,  Y02T90/34 ,  Y10T477/26

Abstract: This invention provides a new method and system to control strategies of a combined fuel cell and battery pack power system to produce an efficient and cost-effective powertrain with acceptable drivability and low emissions. The method and system provide strategies for vehicle start-up, power load changes, and steady state driving conditions. The strategies reduce vehicle maintenance cost by increasing the battery service life and fuel efficiency. Further, the strategies reduce vehicle cost by reducing fuel cell engine size required by a hybrid electric vehicle while responding rapidly to load changes. The strategies also provide increased fuel efficiency by recovery, storage, and re-use of the vehicle kinetic energy normally dissipated as heat during braking.

Abstract translation: 本发明提供了一种新的方法和系统，用于控制组合燃料电池和电池组电力系统的策略，以产生具有可接受的驾驶性能和低排放的高效且具有成本效益的动力系。 该方法和系统提供了车辆起动，动力负载变化和稳态驾驶条件的策略。 该策略通过提高电池使用寿命和燃油效率来降低车辆维护成本。 此外，该策略通过减少混合电动车辆所需的燃料电池发动机尺寸，同时快速响应负载变化来降低车辆成本。 该策略还通过回收，储存和再利用通常在制动过程中散热的车辆动能来提高燃油效率。

公开(公告)号：US06480641B1

公开(公告)日：2002-11-12

申请号：US09434866

申请日：1999-11-04

Applicant: Yi Ding ,  Mario J. Paniccia ,  Timothy J. Maloney

Inventor： Yi Ding ,  Mario J. Paniccia ,  Timothy J. Maloney

IPC: G02B612

CPC classification number: G02F1/218 ,  G02B2006/12107 ,  G02B2006/12142 ,  G02F2001/0152 ,  G02F2201/307

Abstract: An optical modulator that modulates light through the back side of a flip chip packaged integrated circuit die. In one embodiment, an optical modulator includes a p-n junction having a side wall that is substantially vertical or perpendicular relative to a surface of the integrated circuit die. A charged region is generated at the p-n junction and is modulated in response to an electrical signal of the integrated circuit die. An optical beam is directed through the back side, of the semiconductor substrate and through the charged region along the side wall p-n junction. The optical beam is deflected off a deflector back through the charged region along the side wall back out the back side. In one embodiment, the side wall p-n junction is provided with a metal oxide semiconductor (MOS) gate structure. In another embodiment, the side wall p-n junction is provided by an n− (or p−) well in a p− (or n−) epitaxy layer of the semiconductor substrate. In one embodiment, the well is a well ring structure. In another embodiment, there are a plurality of wells periodically located in the epitaxy layer of the semiconductor substrate. In one embodiment, the well or plurality of wells are surrounded with an optical beam confinement structure.

Abstract translation: 一种光调制器，其通过倒装芯片封装的集成电路管芯的背面调制光。 在一个实施例中，光调制器包括具有相对于集成电路管芯的表面基本垂直或垂直的侧壁的p-n结。 在p-n结处产生带电区域，并且响应于集成电路管芯的电信号进行调制。 光束被引导通过半导体衬底的背面，并沿着侧壁p-n结通过带电区域。 光束从背面向后偏转穿过穿过带电区域的偏转器。 在一个实施例中，侧壁p-n结设置有金属氧化物半导体（MOS）栅极结构。 在另一个实施例中，侧壁p-n结由半导体衬底的p-（或n-）外延层中的n-（或p-）阱提供。 在一个实施例中，井是井环结构。 在另一个实施例中，存在周期性地位于半导体衬底的外延层中的多个阱。 在一个实施例中，阱或多个阱被光束约束结构包围。

公开(公告)号：US06421473B1

公开(公告)日：2002-07-16

申请号：US09676297

申请日：2000-09-28

Applicant: Mario J. Paniccia ,  Yi Ding ,  Dmitri E. Nikonov

Inventor： Mario J. Paniccia ,  Yi Ding ,  Dmitri E. Nikonov

IPC: G02B612

CPC classification number: G02F1/025 ,  G02B2006/12145 ,  G02F1/313

Abstract: A device for confining an optical beam in an optical switch. In one embodiment, the disclosed optical switch includes an optical switching device disposed between an optical input port and an optical output port in a semiconductor substrate layer of an integrated circuit die. The semiconductor substrate layer is disposed between a plurality of optical confinement layers such that an optical beam is confined to remain within the semiconductor substrate layer until exiting through the optical output port. In one embodiment, a plurality of semiconductor substrate layers are included in the optical switch. Each of the semiconductor substrate layers is disposed between optical confinement layers such that optical beams passing through the semiconductor substrate layers are confined to remain within the semiconductor substrate layers until exiting through respective optical output ports. In one embodiment, at least one optical switching device is disposed in each of the plurality of semiconductor substrate layers. In one embodiment, integrated circuitry such as driver circuitry, controller circuitry, logic circuitry, coder-decoder circuitry, microprocessor circuitry or the like is included in at least one of the semiconductor substrate layers.

Abstract translation: 用于将光束限制在光开关中的装置。 在一个实施例中，所公开的光开关包括设置在集成电路管芯的半导体衬底层中的光输入端口和光输出端口之间的光开关器件。 半导体衬底层设置在多个光学限制层之间，使得光束被限制为保持在半导体衬底层内，直到通过光学输出端口离开。 在一个实施例中，光开关中包括多个半导体衬底层。 每个半导体衬底层设置在光学限制层之间，使得通过半导体衬底层的光束被限制为保留在半导体衬底层内，直到通过相应的光学输出端口离开。 在一个实施例中，至少一个光学开关器件设置在多个半导体衬底层的每一个中。 在一个实施例中，诸如驱动器电路，控制器电路，逻辑电路，编码器 - 解码器电路，微处理器电路等的集成电路被包括在至少一个半导体衬底层中。