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    Immersion Lithography System Using A Sealed Wafer Bath
    161.
    发明申请
    Immersion Lithography System Using A Sealed Wafer Bath 有权
    浸入式平版印刷系统使用密封晶片浴

    公开(公告)号：US20080106710A1

    公开(公告)日：2008-05-08

    申请号：US11670860

    申请日：2007-02-02

    Applicant: Burn Jeng Lin ,  Ching-Yu Chang

    Inventor： Burn Jeng Lin ,  Ching-Yu Chang

    IPC: G03B27/52

    CPC classification number: G03B27/52 ,  G03F7/70341

    Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus including a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly and comprising a seal ring for sealing a gap between a bottom edge of a wafer retained on the wafer stage and the wafer stage. The apparatus further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid; a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank; and at least one directional flow control fluid inlet surrounding the imaging lens for directing immersion fluid toward an edge of the wafer retained on the wafer stage closest to the imaging lens.

    Abstract translation: 描述了浸没光刻系统和使用密封晶片底部的方法。 一个实施例是一种浸没式光刻设备，其包括透镜组件，该透镜组件包括成像透镜和用于将晶片保持在透镜组件下方的晶片台，并且包括密封环，用于密封保留在晶片台上的晶片的底部边缘与 晶圆台。 该装置还包括用于保持浸没流体的流体箱，相对于晶片台定位的流体箱，用于使保留在晶片台上的晶片能够完全浸入浸没流体中; 设置在所述流体箱的至少一部分上的盖，用于在所述流体箱内提供温度控制的，富含流体的环境; 以及围绕成像透镜的至少一个方向流量控制流体入口，用于将浸没流体引向保持在最靠近成像透镜的晶片台上的晶片的边缘。

    APPARATUS AND METHOD FOR IMMERSION LITHOGRAPHY
    162.
    发明申请
    APPARATUS AND METHOD FOR IMMERSION LITHOGRAPHY 有权
    装置和方法

    公开(公告)号：US20080002164A1

    公开(公告)日：2008-01-03

    申请号：US11697469

    申请日：2007-04-06

    Applicant: Ching-Yu Chang ,  Burn Jeng Lin

    Inventor： Ching-Yu Chang ,  Burn Jeng Lin

    IPC: G03B27/00 ,  B08B3/12

    CPC classification number: B08B3/12 ,  G03F7/2041 ,  G03F7/70341 ,  G03F7/70925

    Abstract: A lithography apparatus includes an imaging lens module, a substrate table positioned underlying the imaging lens module and configured to hold a substrate, and a cleaning module adapted to clean the lithography apparatus. The cleaning module comprises one inlet and one outlet for providing a cleaning fluid to and from a portion of the lithography apparatus to be cleaned, and an ultrasonic unit configured to provide ultrasonic energy to the cleaning fluid.

    Abstract translation: 光刻设备包括成像透镜模块，位于成像透镜模块下方并构造成保持基板的基板台，以及适于清洁光刻设备的清洁模块。 清洁模块包括一个入口和一个出口，用于向待清洁的光刻设备的一部分提供清洁流体;以及超声波单元，被配置为向清洁流体提供超声波能量。

    Method of reducing critical dimension bias of dense pattern and isolation pattern
    165.
    发明授权
    Method of reducing critical dimension bias of dense pattern and isolation pattern 有权
    降低密集图案和隔离图案的关键尺寸偏差的方法

    公开(公告)号：US07097945B2

    公开(公告)日：2006-08-29

    申请号：US10249559

    申请日：2003-04-18

    Applicant: Ching-Yu Chang ,  Hsin-huei Chen ,  Meng-Wei Chen

    Inventor： Ching-Yu Chang ,  Hsin-huei Chen ,  Meng-Wei Chen

    IPC: G03F1/00 ,  H01L21/302

    CPC classification number: G03F1/70

    Abstract: A method of reducing a critical dimension (“CD”) bias between a dense pattern and an isolation pattern is disclosed. The method includes a first step of providing a mask having a dense pattern, an isolation pattern and the other area of the mask is transparent, in which mask the dense pattern has a first opaque pattern and the isolation pattern has a second opaque pattern. The second step of the method is forming a virtual pattern around the isolation pattern, in which a distance between the virtual pattern and the isolation pattern is y, and the virtual pattern has a pattern line width x. By forming the virtual pattern around the isolation pattern, the flare effect of the isolation pattern is close to that of the dense pattern, thus the CD bias between a dense pattern, and an isolation pattern is reduced, and the process window does not shrink.

    Abstract translation: 公开了一种降低致密图案和隔离图案之间的临界尺寸（“CD”）偏压的方法。 该方法包括提供具有致密图案的掩模，隔离图案和掩模的另一区域是透明的第一步骤，其中密集图案具有第一不透明图案，并且隔离图案具有第二不透明图案。 该方法的第二步是在隔离图案周围形成虚拟图案，其中虚拟图案和隔离图案之间的距离为y，虚拟图案具有图案线宽度x。 通过在隔离图案周围形成虚拟图案，隔离图案的耀斑效应接近密集图案的闪光效果，因此减小密集图案和隔离图案之间的CD偏差，并且处理窗口不缩小。

    Hot plate cooling system
    166.
    发明授权
    Hot plate cooling system 有权

    公开(公告)号：US07051800B2

    公开(公告)日：2006-05-30

    申请号：US09727946

    申请日：2000-12-01

    Applicant: Ching-Yu Chang ,  I-Pien Wu

    Inventor： Ching-Yu Chang ,  I-Pien Wu

    IPC: F28F3/12

    CPC classification number: H01L21/67109 ,  F28F3/12

    Abstract: A cooling system for a hot plate. The cooling system includes a plurality of pipelines inside the hot plate. Each pipeline has an inlet and an outlet. The inlet permits a cooling fluid to enter and the outlet permits the cooling fluid to leave. The cooling fluid running inside the pipelines picks up heat from the hot plate and carries away so that the hot plate is cooled.

    Method of forming a dual-layer resist and application thereof
    168.
    发明授权
    Method of forming a dual-layer resist and application thereof 有权
    形成双层抗蚀剂的方法及其应用

    公开(公告)号：US06908854B2

    公开(公告)日：2005-06-21

    申请号：US10715413

    申请日：2003-11-19

    Applicant: Ching-Yu Chang

    Inventor： Ching-Yu Chang

    IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/112 ,  H01L21/4763

    CPC classification number: H01L27/112 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76825 ,  H01L27/11253 ,  Y10S438/948 ,  Y10S438/949

    Abstract: A method of forming a dual-layer resist and application thereof. With respect to the method of forming a dual-layer resist, first, a patterned first resist layer is formed on a substrate. Next, the first resist layer is cured so that the first resist layer does not dissolve in a resist solvent. Finally, a patterned second resist layer is formed on the cured first resist layer. The method of forming a dual-layer resist can be applied to mask ROM coding, hole formation and a dual damascene structure.

    Abstract translation: 一种形成双层抗蚀剂的方法及其应用。 关于形成双层抗蚀剂的方法，首先，在基板上形成图案化的第一抗蚀剂层。 接下来，使第一抗蚀剂层固化，使得第一抗蚀剂层不溶于抗蚀剂溶剂。 最后，在固化的第一抗蚀剂层上形成图案化的第二抗蚀剂层。 可以应用形成双层抗蚀剂的方法来掩蔽ROM编码，孔形成和双镶嵌结构。

    Planarization method using anisotropic wet etching
    169.
    发明授权
    Planarization method using anisotropic wet etching 有权
    使用各向异性湿蚀刻的平面化方法

    公开(公告)号：US06787056B2

    公开(公告)日：2004-09-07

    申请号：US10067260

    申请日：2002-02-07

    Applicant: Wen-Bin Tsai ,  Ching-Yu Chang ,  Chun-Pei Wu ,  Huei-Huang Chen ,  Samuel C. Pan

    Inventor： Wen-Bin Tsai ,  Ching-Yu Chang ,  Chun-Pei Wu ,  Huei-Huang Chen ,  Samuel C. Pan

    IPC: B44C122

    CPC classification number: H01L21/31055 ,  H01L21/31111

    Abstract: A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.

    Abstract translation: 可以应用使用各向异性蚀刻的平面化方法来平坦化具有基板上的不平坦表面的绝缘层。 将H 2 SO 4，H 3 PO 4，HF和H 2 O混合以形成蚀刻溶液。 将衬底放置在蚀刻溶液中以使蚀刻溶液以流速通过绝缘层的表面以蚀刻绝缘层。 经过一段时间的蚀刻时间后，可获得具有更平坦表面的绝缘层。

    Mask ROM structure having a coding layer between gates and word lines
    170.
    发明授权
    Mask ROM structure having a coding layer between gates and word lines 有权
    掩模ROM结构在门和字线之间具有编码层

    公开(公告)号：US06777762B2

    公开(公告)日：2004-08-17

    申请号：US10065645

    申请日：2002-11-05

    Applicant: Ching-Yu Chang

    Inventor： Ching-Yu Chang

    IPC: H01L2994

    CPC classification number: H01L27/112 ,  H01L27/1124

    Abstract: A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the buried bit lines and between the gates, a plurality of word lines each disposed over a row of gates perpendicular to the buried bit lines, and a coding layer between the word lines and the gates.

    Abstract translation: 描述了掩模ROM及其制造方法。 掩模ROM包括衬底，衬底上的多个栅极，栅极和衬底之间的栅极氧化物层，在栅极之间的衬底中的多个掩埋位线，掩埋位线上的绝缘体和栅极之间 ，多个字线，各自设置在与掩埋位线垂直的一行栅极上，以及在字线和栅极之间的编码层。

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