公开(公告)号：US06898099B1

公开(公告)日：2005-05-24

申请号：US10679073

申请日：2003-10-02

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

Abstract translation: 内容可寻址存储器（CAM）架构。 对于一个实施例，CAM架构包括多个CAM单元行，每行被配置为在对应的匹配线上生成匹配结果，多个比较线，每个耦合到多行行中的每一行中的相应CAM单元 CAM单元，多个定时存储电路，每个具有耦合到对应匹配线的数据输入并具有耦合到使能信号线的使能输入的定时存储电路;定时发生器，被配置为在使能信号线上产生使能信号;以及 多个负载元件。

公开(公告)号：US06892272B1

公开(公告)日：2005-05-10

申请号：US10131370

申请日：2002-04-23

Applicant: Varadarajan Srinivasan ,  Ramagopal Madamala

Inventor： Varadarajan Srinivasan ,  Ramagopal Madamala

IPC: G11C15/04 ,  G06F12/00

CPC classification number: G11C15/04

Abstract: A method and apparatus for determining a longest prefix match in a content addressable memory (CAM) device is described. The CAM device includes a CAM array that may be arbitrarily loaded with CIDR addresses that are not prearranged prior to their entry into the CAM device. For one embodiment, the CAM array is a ternary CAM array that includes CAM cells storing CAM data, mask cells storing prefix mask data for the corresponding CAM cells, a CAM match line for indicating a match between a search key and the CAM data (as masked by the prefix mask data), prefix match lines, and prefix logic circuits for comparing the CAM match line with the prefix mask data. The prefix logic circuits determine the longest prefix among the CAM locations that match the search key, regardless of where the matching locations are logically located in the CAM array. The longest prefix is then compared against the prefix mask data stored in the mask cells to determine the location in the CAM array that stores the CIDR address corresponding to the longest prefix. The CAM index or address of the matching CIDR address may then be output from the CAM device. Additionally and/or alternatively, additional or associated data stored at the CAM index may be accessed. The additional or associated data may be, for example, routing information for the stored CIDR address.

Abstract translation: 描述了用于在内容可寻址存储器（CAM）设备中确定最长前缀匹配的方法和装置。 CAM设备包括CAM阵列，其可以任意加载在进入CAM设备之前未被预先安排的CIDR地址。 对于一个实施例，CAM阵列是三元CAM阵列，其包括存储CAM数据的CAM单元，存储对应的CAM单元的前缀掩码数据的掩码单元，用于指示搜索关键字和CAM数据之间的匹配的CAM匹配线 由前缀掩码数据掩蔽），前缀匹配行和用于将CAM匹配行与前缀掩码数据进行比较的前缀逻辑电路。 前缀逻辑电路确定与搜索键匹配的CAM位置中最长的前缀，而不管匹配位置在逻辑上位于CAM阵列中的位置。 然后将最长的前缀与存储在掩码单元中的前缀掩码数据进行比较，以确定存储与最长前缀相对应的CIDR地址的CAM阵列中的位置。 然后可以从CAM设备输出匹配的CIDR地址的CAM索引或地址。 附加地和/或替代地，可以访问存储在CAM索引处的附加或相关联的数据。 附加的或相关联的数据可以是例如存储的CIDR地址的路由信息​​。

公开(公告)号：US06867989B1

公开(公告)日：2005-03-15

申请号：US10207306

申请日：2002-07-29

Applicant: Rupesh Roy

Inventor： Rupesh Roy

IPC: G11C11/412 ,  G11C15/00 ,  G11C15/04

CPC classification number: G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A content addressable memory (CAM) cell including a memory cell coupled to a word line, a compare circuit coupled to the memory cell and to a match line, and a driver circuit having an input coupled to the match line and an output coupled to the word line.

Abstract translation: 一种内容可寻址存储器（CAM）单元，包括耦合到字线的存储器单元，耦合到存储单元和匹配线的比较电路，以及具有耦合到匹配线的输入端的驱动器电路和耦合到 字线。

公开(公告)号：US20020129199A1

公开(公告)日：2002-09-12

申请号：US10025661

申请日：2001-12-18

Applicant: Netlogic Microsystems, Inc.

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G06F012/00

CPC classification number: G11C15/00

Abstract: A content address memory (CAM) device that implements a read next highest priority or nullRNHPMnull instruction. The CAM device initially searches its CAM locations for a match with comparand data. If multiple matches are identified, then the CAM device initially outputs the highest priority matching address. The CAM device may output the highest priority matching address in the same system or clock cycle in which the compare instruction was provided. The CAM device may also output data stored in one or more of the CAM cells located at the highest priority matching location and/or status information including the match flags, a full flag, validity bits (e.g., skip and empty bits), and other status information. An RNHPM instruction may then be provided to the CAM device in the next clock cycle or a later clock cycle and cause the next highest priority matching address to be output by the CAM device. The next highest priority matching address may be output in the same or subsequent cycle as the RNHPM instruction and may also cause the CAM device to output data stored in one or more of the CAM cells located at the next highest priority matching location and/or status information for that location. RNHPM instructions can continue to be supplied to the CAM device until no further matching locations are detected.

Abstract translation: 实现读取下一个最高优先级或“RNHPM”指令的内容地址存储器（CAM）设备。 CAM设备最初搜索其CAM位置以获得与比较数据的匹配。 如果识别出多个匹配，则CAM设备最初输出最高优先级匹配地址。 CAM设备可以在提供比较指令的相同系统或时钟周期中输出最高优先级的匹配地址。 CAM设备还可以输出存储在位于最高优先级匹配位置的一个或多个CAM单元中的数据和/或包括匹配标志的状态信息，完整标志，有效位（例如，跳过和空位）等的数据 状态信息。 然后可以在下一个时钟周期或更晚的时钟周期中向CAM设备提供RNHPM指令，并且使CAM设备输出下一个最高优先级的匹配地址。 可以在与RNHPM指令相同或随后的周期中输出下一个最高优先级的匹配地址，并且还可以使CAM设备输出存储在位于下一个最高优先级匹配位置和/或状态的一个或多个CAM单元中的数据 该位置的信息。 RNHPM指令可以继续提供给CAM设备，直到没有检测到更多的匹配位置为止。

公开(公告)号：US20150074442A1

公开(公告)日：2015-03-12

申请号：US14024063

申请日：2013-09-11

Applicant: NetLogic Microsystems, Inc.

Inventor： Ahmed SHAHID ,  Kaushik Kuila ,  David T. Hass

IPC: G06F1/00

CPC classification number: G06F1/00 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0667 ,  H04J3/0685

Abstract: A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

Abstract translation: 提供了一种用于减少与多核，多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心，多个用于网络通信的网络接口，以及定时器电路，用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。

公开(公告)号：US08913412B1

公开(公告)日：2014-12-16

申请号：US13306896

申请日：2011-11-29

Applicant: Sandeep Khanna ,  Bindiganavale S. Nataraj ,  Varadarajan Srinivasan

Inventor： Sandeep Khanna ,  Bindiganavale S. Nataraj ,  Varadarajan Srinivasan

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and an incremental match line charge circuit. The detector circuit generates a feedback signal based on a detected match line voltage. The charge circuit partially pre-charges the match line to an intermediate voltage during a pre-charge phase of a compare operation, and then selectively charges the match line higher towards a supply voltage in response to the feedback signal.

Abstract translation: 具有任意行数的内容可寻址存储器（CAM）器件，每行包括连接到多个CAM单元的匹配线，匹配线检测器电路和增量匹配线充电电路。 检测器电路基于检测到的匹配线电压产生反馈信号。 充电电路在比较操作的预充电阶段期间将匹配线部分预充电到中间电压，然后响应于反馈信号而选择性地将匹配线充电到电源电压。

公开(公告)号：US08886677B1

公开(公告)日：2014-11-11

申请号：US11768646

申请日：2007-06-26

Applicant: Gary Depelteau ,  David W. Carr

Inventor： Gary Depelteau ,  David W. Carr

IPC: G06F17/30

CPC classification number: G06F17/30327

Abstract: A pipelined search engine supports a tree of search keys therein that utilizes span prefix masks to assist in longest prefix match (LPM) detection when the tree is searched. Each of a plurality of the span prefix masks encodes a prefix length of a search key to which the span prefix mask is associated and a value of another search key in the tree that is a prefix match to the search key to which the span prefix mask is associated.

Abstract translation: 流水线搜索引擎支持其中的搜索关键字树，其利用跨越前缀掩码以在搜索树时辅助最长前缀匹配（LPM）检测。 多个跨度前缀掩码中的每一个编码与跨度前缀掩码相关联的搜索关键字的前缀长度，并且作为前缀的树中的另一个搜索关键字的值与搜索关键字匹配，跨度前缀掩码 已关联的。

公开(公告)号：US08787059B1

公开(公告)日：2014-07-22

申请号：US13311301

申请日：2011-12-05

Applicant: Vinay Iyengar

Inventor： Vinay Iyengar

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/10 ,  G06F17/30

CPC classification number: G11C15/04 ,  G06F17/30982 ,  G11C7/1048 ,  G11C15/00

Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.

Abstract translation: 内容可寻址存储器（CAM）设备具有包括被划分成行段的多个CAM行的阵列，其中相应的行包括第一行段，其包括耦合到第一匹配线段的多个第一CAM单元，第二行段 行段，其包括耦合到第二匹配线段的多个第二CAM单元，以及电路，用于响应于指示存储在相应行的第一行段中的数据是否为第一匹配线段的值是有选择地预充电第一匹配线段 与存储在另一行的第一行段中的数据相同。 在比较操作期间可以减少功耗，其中存储与相应行的第一行段相同的数据的另一行的第一行段不被启用。

公开(公告)号：US20140185593A1

公开(公告)日：2014-07-03

申请号：US14196804

申请日：2014-03-04

Applicant: NetLogic Microsystems, Inc.

Inventor： Yan WANG

IPC: H04L5/00

CPC classification number: H04L5/0058 ,  G06F3/00 ,  G06F9/46 ,  G06F13/14 ,  G06F13/3625 ,  G06F13/4031 ,  G06F15/17325

Abstract: A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.

Abstract translation: 一种处理系统包括芯片间接口，其包括具有仲裁器的芯片间接口模块，所述仲裁器在每个固定数量的时间片中分配专用时间片，以分配第一优先级以从具有 专用时间片内存储器中的第一个数据路径宽度。 在固定数量的时间片的剩余时间片中，仲裁器进一步在除第一类型之外的一种或多种类型的多个信道之中进行仲裁，其中多个信道对应于与第一数据路径宽度不同的至少一个数据路径宽度，以及 具有更广泛数据通路的通道赢得仲裁。 如果某种类型的信道在时间片中赢得仲裁，仲裁者将进一步仲裁相同类型的两个或多个信道。 还公开了其实现方法。

公开(公告)号：US08725919B1

公开(公告)日：2014-05-13

申请号：US13164319

申请日：2011-06-20

Applicant: Julianne J. Zhu ,  David T. Hass

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: G06F13/00

CPC classification number: G06F9/4411 ,  G06F13/102 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

Abstract translation: 公开了一种用于配置用于多处理器系统的设备的方法，其中属于不同处理器的设备被视为连接到标准化公共总线。 无论设备直接连接到哪个特定处理器，该设备一般可以通过标准化的公共总线进行识别和访问。 PCIe是可以采用的合适的标准总线类型的示例，其中用于每个处理器节点的设备被表示为PCIe设备。 因此，每个设备将作为PCIe设备出现在系统软件中。 然后可以使用PCIe控制器通过参考适当的设备标识符来访问设备。 这允许在任何处理器节点上访问任何设备，而对于每个单独的处理器节点没有单独和个性化的配置或驱动程序。