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公开(公告)号：US20230343837A1
公开(公告)日：2023-10-26
申请号：US17771468
申请日：2022-04-20
Inventor： Yuanpeng CHEN
IPC: H01L29/417 , H01L29/786
CPC classification number: H01L29/41733 , H01L29/7869
Abstract: The present application provides a display panel and a display device. The display panel comprises a substrate and a thin film transistor layer disposed on the substrate, wherein the thin film transistor layer comprises an active layer and a metal layer that are stacked, and the active layer comprises an active segment and a conductor segment connected to the active segment; and wherein the conductor segment comprises a lap portion connected to the metal layer and a conductor sub-segment between the lap portion and the active segment, and a groove is formed in the conductor sub-segment.
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公开(公告)号：US20230335028A1
公开(公告)日：2023-10-19
申请号：US17438449
申请日：2021-07-16
Inventor： Deyan LI , Jianhong CHEN , Peng DU , Xiaoming CHEN
CPC classification number: G09G3/20 , H01L27/124 , G09G2300/0408 , G09G2310/0202 , G09G2310/0267 , G09G2320/02
Abstract: The embodiment of the present disclosure provides a display panel and a display apparatus. The display panel includes a long side, a short side, a display pixel, a scan driving circuit, a drive circuit board, and chips on film. one end of each chip on film is coupled to the short side, and another end is coupled to the drive circuit board. The drive circuit board and the scan driving circuit of the embodiment of the present disclosure are respectively located on the short side and the long side of the display panel to improve the problem that the font is easily deformed during display.
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公开(公告)号：US11791352B2
公开(公告)日：2023-10-17
申请号：US17057663
申请日：2020-10-30
Inventor： Wei Cui , Miao Jiang , Jiangbo Yao , Lixuan Chen , Xin Zhang
IPC: H01L27/144 , G06F3/042 , H01L31/101 , H01L31/113 , H10K59/60
CPC classification number: H01L27/1443 , G06F3/0421 , H01L27/1446 , H01L31/1013 , H01L31/1136 , H10K59/60
Abstract: The present application provides a display panel and a display device. The display panel includes a plurality of light-sensing circuits and a position detection circuit. The plurality of light-sensing circuits are disposed in the display panel and are arranged in an array. Each of the plurality of light-sensing circuits includes a light-sensing transistor. The present application disposes a quantum dot layer, which can absorb interactive light and convert its light intensity signal into an electrical signal, and determines an irradiation position of the interactive light through the position detection circuit, so that an interaction with light with a longer wavelength can be realized.
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公开(公告)号：US11734483B2
公开(公告)日：2023-08-22
申请号：US17048596
申请日：2020-08-12
Inventor： Yang Liu
IPC: G06F30/392 , G06F30/31
CPC classification number: G06F30/392 , G06F30/31
Abstract: A method of driving design on gate electrodes includes steps of: determining position information of a gate-on-array (GOA) device in an available drawing space according to a size design information and a resolution design information of a display panel, based on user configuration; determining target GOA design strategy information used for a current gate electrode driving design among a plurality of preset GOA design strategies; and drawing a GOA device pattern in the available drawing space of the GOA device, based on the target GOA design strategy information.
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公开(公告)号：US20230257218A1
公开(公告)日：2023-08-17
申请号：US17419034
申请日：2020-12-29
Inventor： Xin Zhang , Hongyuan Xu , Jia Li
CPC classification number: B65G49/067 , B65G49/0427 , B65G49/061 , B65G2249/045
Abstract: A fabrication platform used for production lines of a display panel is provided. The fabrication platform includes: a jig, wherein the jig is configured to carry a glass substrate, and a plurality of via holes are defined on the jig; and an adsorption device, wherein the adsorption device includes a plurality of suction pads, the suction pads are disposed on a side of the jig away from the glass substrate and are disposed corresponding to the via holes, and the suction pads adsorb the glass substrate on the jig through the via holes. The provided fabrication platform effectively improves yield rate of the glass substrate in welding processes.
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Patent Agency Ranking
公开(公告)号：US20230238401A1
公开(公告)日：2023-07-27
申请号：US17598868
申请日：2021-07-09
Applicant: HUIZHOU CHINA STAR OPTOELECTRONICS DISPLAY CO., LTD. , SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
Inventor： Macai Lu
CPC classification number: H01L27/1251 , H01L33/62 , H01L27/127 , H01L33/505 , H01L25/167 , H01L2933/0066 , H01L2933/0041
Abstract: An embodiment of the application discloses a panel and a manufacturing method thereof. In the panel, a thin-film transistor layer, a first conductive layer, a light-emitting diode (LED), and a second conductive layer are sequentially disposed on a substrate. The LED includes a first end and a second end. The first end is disposed on the first electrode. The second end is disposed on the second electrode. The second conductive layer includes a first conductive portion and a second conductive portion. The first conductive portion is electrically connected to the first end and the first electrode. The second conductive portion is electrically connected to the second end and the second electrode.
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公开(公告)号：US20230229043A1
公开(公告)日：2023-07-20
申请号：US17637086
申请日：2022-01-25
Inventor： Mingming LI , Baixiang HAN
IPC: G02F1/1345
CPC classification number: G02F1/13452
Abstract: A display panel and a display device are provided. The display panel has a first area, a second area, and a third area arranged in sequence. The display panel includes a substrate, a plurality of first wirings, and a plurality of second wirings. The first wirings extend from the first area to the second area. The second wirings extend from the second area to the third area. The first wirings and the second wirings are arranged in different layers. The first wirings and the second wirings are connected in a one-to-one correspondence through via holes. The via holes are staggered in the second area.
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公开(公告)号：US11694618B2
公开(公告)日：2023-07-04
申请号：US17253137
申请日：2020-03-27
Inventor： Yan Xue
IPC: G09G3/3233 , G09G3/3266 , G09G3/3291
CPC classification number: G09G3/3233 , G09G3/3266 , G09G3/3291 , G09G2300/0819 , G09G2330/021
Abstract: A pixel driving circuit and a display panel are provided, and adopt a pixel driving circuit of 5T1C structure to effectively compensate the threshold voltage of the driving transistor in each pf the pixels. The pixel driving circuit can effectively reduce leakage power consumption of a pixel driving circuit when extracting a threshold voltage, thereby improving compensation accuracy of the pixel driving circuit.
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公开(公告)号：US20230205025A1
公开(公告)日：2023-06-29
申请号：US17438658
申请日：2021-07-23
Inventor： Yoonsung UM , Lixia LI , Bangyin PENG , Yingchun ZHAO , Fen LONG , Qiqi ZHANG
IPC: G02F1/1362 , G02F1/1368
CPC classification number: G02F1/136286 , G02F1/136209 , G02F1/1368
Abstract: A liquid crystal display panel and a display device are disclosed. The liquid crystal display panel includes a pixel matrix composed of more than two sub-pixels. Three adjacent sub-pixels located in the same row have different colors, and all sub-pixels located in the same column have the same color. Each data line is connected to at least one pixel group successively. Each pixel group includes three sub-pixels with different colors, which are respectively located on both sides of the data line. In a pixel group, each data line is connected to three sub-pixels in sequence.
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公开(公告)号：US20230197738A1
公开(公告)日：2023-06-22
申请号：US17624033
申请日：2021-12-27
Inventor： Chen DAI
IPC: H01L27/12
CPC classification number: H01L27/1251 , H01L27/1225 , H01L27/1262
Abstract: An array substrate, a display panel, and a manufacturing method of the array substrate are disclosed. The array substrate includes a substrate and a thin film transistor layer. The thin film transistor layer includes a first thin film transistor, and the first thin film transistor includes a first active layer, a first gate insulating layer, a first source and drain electrode layer, and a first gate electrode disposed on a same layer as the first source and drain electrode layer. Disposing the first gate electrode on the same layer as the first source and drain electrode layer can simplify manufacturing processes.
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