公开(公告)号：US20230170264A1

公开(公告)日：2023-06-01

申请号：US17995791

申请日：2021-03-29

Applicant: Soitec

Inventor： Trong Hyunh-Bao ,  Bich-Yen Nguyen ,  Christophe Maleville

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/42376 ,  H01L21/76281

Abstract: A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

公开(公告)号：US20230129131A1

公开(公告)日：2023-04-27

申请号：US17452197

申请日：2021-10-25

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Gweltaz Gaudin

IPC: G02B6/132 ,  G02B6/136 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

公开(公告)号：US20230025429A1

公开(公告)日：2023-01-26

申请号：US17757822

申请日：2021-01-07

Applicant: Soitec

Inventor： Aymen Ghorbel ,  Frédéric Allibert ,  Damien Massy ,  Isabelle Bertrand ,  Lamia Nouri

IPC: H01L21/761 ,  H01L21/762

Abstract: The invention relates to a method for manufacturing a semiconductor-on-insulator structure (10), comprising the following steps: —providing an FD-SOI substrate (1) comprising, successively from its base to its top: a monocrystalline substrate (2) having an electrical resistivity of between 500 Ω·cm and 30 kΩ·cm, an interstitial oxygen content (Oi) of between 20 and 40 old ppma, and having an N- or P-type doping, an electrically insulating layer (3) having a thickness of between 20 nm and 400 nm, a monocrystalline layer (4) having a P-type doping, —heat-treating the FD-SOI substrate (1) at a temperature greater than or equal to 1175° C. for a time greater than or equal to 1 hour in order to form a P-N junction (5) in the substrate. The invention also relates to such a semiconductor-on-insulator structure.

公开(公告)号：US11557715B2

公开(公告)日：2023-01-17

申请号：US16759992

申请日：2018-10-31

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Jean-Marc Bethoux

IPC: H01L41/313 ,  H01L21/265 ,  H01L41/187

Abstract: A method for manufacturing a film, notably monocrystalline, on a flexible sheet, comprises the following steps: providing a donor substrate, forming an embrittlement zone in the donor substrate so as to delimit the film, forming the flexible sheet by deposition over the surface of the film, and detaching the donor substrate along the embrittlement zone so as to transfer the film onto the flexible sheet.

公开(公告)号：US20220415653A1

公开(公告)日：2022-12-29

申请号：US17756609

申请日：2020-10-26

Applicant: Soitec

Inventor： Hugo Biard

IPC: H01L21/02 ,  H01L21/306 ,  C30B29/36 ,  C30B25/20 ,  C23C14/48 ,  C23C16/448 ,  C23C16/32 ,  C23C16/56 ,  C23C16/01

Abstract: A process for manufacturing a composite structure comprises: a) providing an initial substrate made of monocrystalline silicon carbide, b) epitaxially growing a monocrystalline silicon carbide donor layer on the initial substrate to form a donor substrate 111, c) implanting ions into the donor layer to form a buried brittle plane defining the the donor layer, d) depositing, using liquid injection-chemical vapor deposition at a temperature below 1000° C., a carrier layer on the donor layer, the carrier layer comprising an at least partially amorphous SiC matrix, e) separating the donor substrate along the brittle plane to form an intermediate composite structure comprising the donor layer on the carrier layer f) heat treating the intermediate composite structure at a temperature of between 1000° C. and 1800° C. to crystallize the carrier layer and form the polycrystalline carrier substrate, and g) applying mechanical and/or chemical treatment(s) of the composite structure.

公开(公告)号：US20220399200A1

公开(公告)日：2022-12-15

申请号：US17755812

申请日：2020-11-25

Applicant: Soitec

Inventor： Young-Pil Kim ,  Isabelle Bertrand ,  Christelle Veytizou

IPC: H01L21/02 ,  H01L41/053 ,  H01L21/762 ,  H01L41/312

Abstract: A method for forming a high resistivity handle substrate for a composite substrate comprises: providing a base substrate made of silicon; exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer having a thickness of at least 10 nm on the surface of the base substrate; and then growing a polycrystalline charge trapping layer on the carbon-containing layer.

公开(公告)号：US20220319910A1

公开(公告)日：2022-10-06

申请号：US17597583

申请日：2020-07-13

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  Soitec

Inventor： Vincent Larrey ,  François Rieutord ,  Jean-Michel Hartmann ,  Frank Fournel ,  Didier Landru ,  Oleg Kononchuk ,  Ludovic Ecarnot

IPC: H01L21/762 ,  H01L21/02

Abstract: A process for hydrophilic bonding first and second substrates, comprising: —bringing the first and second substrates into contact to form a bonding interface between main surfaces of the first and second substrates, and —applying a heat treatment to close the bonding interface. The process further comprises, before the step of bringing into contact, depositing, on the main surface of the first and/or second substrate, a bonding layer comprising a non-metallic material that is permeable to dihydrogen and that has, at the temperature of the heat treatment, a yield strength lower than that of at least one of the materials of the first substrate and of the second substrate located at the bonding interface. The layer has a thickness between 1 and 6 nm, and the heat treatment is carried out at a temperature lower than or equal to 900° C., and preferably lower than or equal to 600° C.

公开(公告)号：US20220181173A1

公开(公告)日：2022-06-09

申请号：US17435899

申请日：2020-02-26

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed

IPC: H01L21/67 ,  H01L21/762

Abstract: A system for fracturing a plurality of wafer assemblies, one of the wafers of each assembly comprising a plane of weakness and each assembly comprising a peripheral lateral groove comprises: a cradle for keeping the assemblies of the plurality of assemblies spaced apart and parallel to one another, along a storage axis; a separation device for applying separating forces in the peripheral groove of an assembly arranged in a fracture zone of the separating device, the separating force aiming to separate the wafers of the assembly from one another so as to initiate its fracture at the plane of weakness; and a drive device configured to move along the storage axis of the cradle opposite the separating device so as to successively place an assembly of the cradle in the fracture zone of the separation device.

公开(公告)号：US11349065B2

公开(公告)日：2022-05-31

申请号：US15769690

申请日：2016-10-17

Applicant: Soitec

Inventor： Didier Landru

IPC: H01L41/313 ,  H03H9/02 ,  H01L41/083 ,  H01L41/053 ,  H01L41/08

Abstract: A method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a′) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c).

公开(公告)号：US20220157882A1

公开(公告)日：2022-05-19

申请号：US17649982

申请日：2022-02-04

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Oleg Kononchuk ,  Ludovic Ecarnot ,  Christelle Michau

IPC: H01L27/146 ,  H01L21/762

Abstract: A substrate for a front-side type image sensor includes a supporting semiconductor substrate, an electrically insulating layer, and a silicon-germanium semiconductor layer, known as the active layer. The electrically insulating layer includes a stack of dielectric and metallic layers selected such that the reflectivity of the stack in a wavelength range of between 700 nm and 3 μm is greater than the reflectivity of a silicon oxide layer having a thickness equal to that of the stack. The substrate also comprises a silicon layer between the electrically insulating layer and the silicon-germanium active layer. The disclosure also relates to a method for the production of such a substrate.