METHOD FOR OPTIMIZING CIRCUIT TIMING BASED ON FLEXIBLE REGISTER TIMING LIBRARY

    公开(公告)号:US20230214567A1

    公开(公告)日:2023-07-06

    申请号:US18011443

    申请日:2022-03-09

    CPC classification number: G06F30/3315 G06F30/337 G06F2119/12

    Abstract: Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

    Method for modeling sequence impedance of modular multilevel converter under phase locked loop coupling

    公开(公告)号:US11687699B2

    公开(公告)日:2023-06-27

    申请号:US17771967

    申请日:2021-12-11

    CPC classification number: G06F30/398 H02J3/381 H02J2203/20

    Abstract: The present invention discloses a method for modeling sequence impedance of a modular multilevel converter (MMC) under phase locked loop (PLL) coupling. The method includes the following steps: S1, establishing a circuit topology model; S2, establishing a PLL output characteristic model; S3, establishing a PI controller output control small signal model under a dq axis; S4, deducing a modulation small signal; and S5, calculating MMC port impedance. According to the method, a precise MMC port impedance model is established by analyzing a double mirror frequency coupling effect in the output of a modulation signal in a control link caused by a phase angle disturbance and comprehensively considering the combination of the multi-harmonic coupling effect of an MMC. On one hand, the proposed modeling method aims at a common MMC adopting current closed-loop control, in which a half-bridge sub-module is adopted, a circuit topological structure and a control structure are both more common, and a mathematical model is easy to establish. On the other hand, the physical significance of an impedance analysis method is clear, the modeling process is modular and is easy to understand and implement, and the inverter port impedance can be measured on site, so that the correctness of theoretical modeling can be conveniently verified.

    FLEXIBLE MODELING METHOD FOR TIMING CONSTRAINT OF REGISTER

    公开(公告)号:US20230195985A1

    公开(公告)日:2023-06-22

    申请号:US18014002

    申请日:2022-03-09

    CPC classification number: G06F30/3312 G06F30/3315 G06F2119/12

    Abstract: Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.

    CHANNEL EQUALIZATION-FREE SINGLE-CARRIER BROADBAND TRANSMISSION METHOD AND SYSTEM

    公开(公告)号:US20230179268A1

    公开(公告)日:2023-06-08

    申请号:US17928431

    申请日:2022-04-13

    CPC classification number: H04B7/043 H04B7/0617

    Abstract: The present invention discloses a channel equalization-free single-carrier broadband transmission method, including the following steps: obtaining a number of temporal-resolvable multi-paths, and delays and channel gain vectors corresponding to the multi-paths based on a channel impulse response; deliberately introducing, by a transmitter, a corresponding delay for a symbol sequence, so as to perform delay compensation, so that all multi-path signal components arrive at a receiver simultaneously and constructively after propagating over a time-dispersive channel, thereby avoiding inter-symbol interference in broadband transmission; and utilizing, by the transmitter, multiple antennas to perform path-based beamforming design. A time-dispersive channel can be transformed into a frequency-flat channel by means of the path-based ZF beamforming and delay alignment modulation. The present invention further proposes a channel equalization-free single-carrier broadband transmission system. In the present invention, with delay alignment modulation and the path-based beamforming, the issue of inter-symbol interference in broadband communications is resolved, without requiring the channel equalization or multi-carrier transmission, thereby achieving the low-complexity single-carrier broadband communication.

    Six-dimensional force sensor with high sensitivity and low inter-dimensional coupling

    公开(公告)号:US11650117B2

    公开(公告)日:2023-05-16

    申请号:US16973690

    申请日:2020-04-22

    CPC classification number: G01L5/1627 G01L1/2262

    Abstract: The present invention discloses a six-dimensional force sensor with high sensitivity and low inter-dimensional coupling, including a clockwise or counterclockwise swastika-shaped beam, vertical beams, a rectangular outer frame, and strain gauges; the clockwise or counterclockwise swastika-shaped beam includes a cross-shaped transverse beam and four rectangular transverse beams; a center of the cross-shaped transverse beam is provided with several force application holes used for applying forces and moments; four tail ends of the cross-shaped transverse beam are each connected to one of the rectangular transverse beams to form a clockwise or counterclockwise swastika-shaped structure; a top end of a vertical beam is connected to a tail end of a corresponding rectangular transverse beam, and bottom ends of the vertical beams are connected to the rectangular outer frame; and there are a plurality of strain gauges to form six groups of Wheatstone bridges that are respectively used for measuring an X-direction force, a Y-direction force, a Z-direction force, an X-direction moment, a Y-direction moment, and a Z-direction moment. Strain gauges for measuring the forces are all pasted on the cross-shaped transverse beam, strain gauges for measuring the X-direction moment and the Y-direction moment are all pasted on the four rectangular transverse beams, and strain gauges for measuring the Z-direction moment are all pasted on the four vertical beams. According to the present invention, the structure is simple, and inter-dimensional coupling is low while high sensitivity is ensured.

    GENE INTERFERENCE VECTOR- AND IRON NANOPARTICLE-BASED COMPOSITION FOR KILLING CANCER CELLS, AND USE THEREOF

    公开(公告)号:US20230143359A1

    公开(公告)日:2023-05-11

    申请号:US17911130

    申请日:2021-01-15

    CPC classification number: A61K33/26 A61K48/0058 A61P35/00

    Abstract: Disclosed in the present invention are a gene interference vector- and iron nanoparticle-based composition for killing cancer cells, and the use thereof. The composition comprises a gene interference vector and iron nanoparticles, wherein the gene interference vector is a CRISPR/Cas13a expression vector or microRNA expression vector controlled by a cancer cell specific promoter DMP, with the Cas13a-gRNA or microRNA expressed by the vector being able to inhibit, in a targeted manner, intracellular iron metabolism and the expression of reactive oxygen related genes, and the iron nanoparticles can be degraded after entering cells to produce iron ions and to increase the reactive oxygen level. The composition comprising the gene interference vector and the iron nanoparticles of the present invention can be used for preparing a new reagent for treating cancers.

    METHOD FOR MODELING SEQUENCE IMPEDANCE OF MODULAR MULTILEVEL CONVERTER UNDER PHASE LOCKED LOOP COUPLING

    公开(公告)号:US20230118255A1

    公开(公告)日:2023-04-20

    申请号:US17771967

    申请日:2021-12-11

    Abstract: The present invention discloses a method for modeling sequence impedance of a modular multilevel converter (MMC) under phase locked loop (PLL) coupling. The method includes the following steps: S1, establishing a circuit topology model; S2, establishing a PLL output characteristic model; S3, establishing a PI controller output control small signal model under a dq axis; S4, deducing a modulation small signal; and S5, calculating MMC port impedance. According to the method, a precise MMC port impedance model is established by analyzing a double mirror frequency coupling effect in the output of a modulation signal in a control link caused by a phase angle disturbance and comprehensively considering the combination of the multi-harmonic coupling effect of an MMC. On one hand, the proposed modeling method aims at a common MMC adopting current closed-loop control, in which a half-bridge sub-module is adopted, a circuit topological structure and a control structure are both more common, and a mathematical model is easy to establish. On the other hand, the physical significance of an impedance analysis method is clear, the modeling process is modular and is easy to understand and implement, and the inverter port impedance can be measured on site, so that the correctness of theoretical modeling can be conveniently verified.

    Method and apparatus for extracting mountain landscape buildings based on high-resolution remote sensing images

    公开(公告)号:US11615615B2

    公开(公告)日:2023-03-28

    申请号:US17153967

    申请日:2021-01-21

    Abstract: The present invention discloses a method and an apparatus for extracting mountain landscape buildings based on high-resolution remote sensing images. The method comprises: segmenting a remote sensing image, and extracting non-vegetation areas from the remote sensing image by using NDVI; segmenting the non-vegetation areas, and extracting building areas by using NDBI; segmenting the building areas again, and calculating a normalized difference build shadow index NSBI of each patch; calculating NSBI separator of each patch in the non-vegetation areas and setting a separator threshold, and extracting landscape building areas based on the threshold. In the present invention, by introducing a near infrared band in the remote sensing image spectrum, in which there is a significant difference between shadows and non-shadows, the influence of large shadow areas in mountainous shady areas in the remote sensing image on the result of extraction is reduced.

    Four-dimensional over the air performance test method for dynamic scene channel

    公开(公告)号:US11611404B2

    公开(公告)日:2023-03-21

    申请号:US17862051

    申请日:2022-07-11

    Abstract: The present disclosure discloses a four-dimensional over the air performance test method for a dynamic scene channel. By constructing a time-domain non-stationary dynamic scene channel model, and selecting over the air (OTA) probes of appropriate number, positions and power weight in a four-dimensional multi-probe anechoic chamber (4D-MPAC) test system through a probe selection algorithm, finally a 4D-MPAC dynamic channel test system for a target channel in a DUT test area is constructed, which makes a contribution to solve the current problem of OTA performance test for a time-domain non-stationary channel. The present disclosure aims to provide a four-dimensional multi-probe anechoic chamber (4D-MPAC) for the dynamic scene channel, which can effectively and accurately reproduce a target dynamic scene channel model in an anechoic chamber on the basis of reducing the cost of the test system as much as possible by constructing the dynamic scene channel model, and provide an index for judging the accuracy of constructing the dynamic scene channel model.

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