公开(公告)号：US08809159B2

公开(公告)日：2014-08-19

申请号：US13722155

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L21/20

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1641

Abstract: Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.

Abstract translation: 提供了辐射增强的电阻式开关层，包括这些层的电阻随机存取存储器（ReRAM）单元，以及形成这些层和单元的方法。 辐射在电阻开关材料中产生缺陷，允许在这些材料中形成和断开导电路径，从而提高其电阻开关特性。 例如，电离辐射可以破坏用于这种层的各种材料中的化学键，而非电离辐射可以形成电子陷阱。 可以控制辐射功率，打盹等处理特性，以产生电阻式开关层内的缺陷分布。 例如，通过层的厚度的缺陷的不均匀分布可能有助于降低开关电压和/或电流。 可以在热退火之前或之后进行辐射，其可以用于控制电阻开关层中辐射产生的缺陷和其他类型的缺陷的分布。

公开(公告)号：US20140175364A1

公开(公告)日：2014-06-26

申请号：US13722155

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1641

Abstract: Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.

Abstract translation: 提供了辐射增强的电阻式开关层，包括这些层的电阻随机存取存储器（ReRAM）单元，以及形成这些层和单元的方法。 辐射在电阻开关材料中产生缺陷，允许在这些材料中形成和断开导电路径，从而提高其电阻开关特性。 例如，电离辐射可以破坏用于这种层的各种材料中的化学键，而非电离辐射可以形成电子陷阱。 可以控制辐射功率，打盹等处理特性，以产生电阻式开关层内的缺陷分布。 例如，通过层的厚度的缺陷的不均匀分布可能有助于降低开关电压和/或电流。 可以在热退火之前或之后进行辐射，其可以用于控制电阻开关层中辐射产生的缺陷和其他类型的缺陷的分布。

公开(公告)号：US20140175356A1

公开(公告)日：2014-06-26

申请号：US13721658

申请日：2012-12-20

Applicant: INTERMOLECULAR INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1293 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元，其包括电阻开关层和用于在操作期间限制来自开关层的散热的热隔离结构。 热隔离结构可以位于堆叠内或邻近堆叠。 例如，堆叠可以包括一个或两个热隔离结构。 热隔离结构可以直接与开关层接口或者可以通过例如电极分离。 热分离结构可以由导热率小于1W / m×K的材料形成，例如多孔二氧化硅和中孔氧化钛。 与开关层串联设置的隔热结构通常具有小于开关层的低电阻状态的电阻。 位于与开关层相邻的隔热结构可具有大于开关层的高电阻状态的电阻。

公开(公告)号：US20140154859A1

公开(公告)日：2014-06-05

申请号：US13705516

申请日：2012-12-05

Applicant: INTERMOLECULAR INC.

Inventor： Vidyut Gopal ,  Tony P. Chiang ,  Imran Hashim ,  Randall J. Higuchi ,  Robert A. Huertas ,  Hieu Pham ,  Yun Wang

IPC: H01L49/02

CPC classification number: H01L22/34 ,  H01L45/08 ,  H01L45/145

Abstract: Provided are methods for processing different materials on the same substrate for high throughput screening of multiple ReRAM materials. A substrate may be divided into multiple site isolated regions, each region including one or more base structures operable as bottom electrodes of ReRAM cells. Different test samples may be formed over these base structures in a combinatorial manner. Specifically, each site isolated region may receive a test sample that has a different characteristic than at least one other sample provided in another region. The test samples may have different compositions and/or thicknesses or be deposited using different techniques. These different samples are then etched in the same operation to form portions of the samples. Each portion is substantially larger than the corresponding base structure and fully covers this base structure to protect the interface between the base structure and the portion during etching.

Abstract translation: 提供了在同一基板上处理不同材料的方法，用于多个ReRAM材料的高通量筛选。 衬底可以被分成多个位置隔离区域，每个区域包括可操作为ReRAM单元的底部电极的一个或多个基底结构。 可以以组合的方式在这些基础结构上形成不同的测试样品。 具体地说，每个位置隔离区域可以接收具有与另一区域中提供的至少一个其他样品不同的特性的测试样品。 测试样品可以具有不同的组成和/或厚度或使用不同的技术沉积。 然后在相同的操作中蚀刻这些不同的样品以形成样品的一部分。 每个部分基本上大于对应的基部结构，并且完全覆盖该基部结构以在蚀刻期间保护基部结构和该部分之间的界面。

公开(公告)号：US20140138602A1

公开(公告)日：2014-05-22

申请号：US14163970

申请日：2014-01-24

Applicant: Intermolecular, Inc.

Inventor： Michael Miller ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L45/00

CPC classification number: H01L45/122 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  H01L21/265 ,  H01L21/322 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1675

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract translation: 描述了用于电阻存储器的受控局部缺陷路径，包括用于形成受控局部缺陷路径的方法，包括形成在第一电极上形成金属氧化物层的第一电极，掩蔽金属氧化物以产生暴露区域和隐藏区域 金属氧化物，并且改变金属氧化物的暴露区域以在暴露区域下方产生局部缺陷路径。

公开(公告)号：US20140134794A1

公开(公告)日：2014-05-15

申请号：US14156762

申请日：2014-01-16

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

公开(公告)号：US20140071435A1

公开(公告)日：2014-03-13

申请号：US14077545

申请日：2013-11-12

Applicant: Intermolecular, Inc.

Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

IPC: G01R31/26 ,  G01N21/55

CPC classification number: G01R31/26 ,  G01N21/55 ,  G01R31/2607 ,  H02S50/10

Abstract: Simultaneous measurement of an internal quantum efficiency and an external quantum efficiency of a solar cell using an emitter that emits light; a three-way beam splitter that splits the light into solar cell light and reference light, wherein the solar cell light strikes the solar cell; a reference detector that detects the reference light; a reflectance detector that detects reflectance light, wherein the reflectance light comprises a portion of the solar cell light reflected off the solar cell; a source meter operatively coupled to the solar cell; a multiplexer operatively coupled to the solar cell, the reference detector, and the reflectance detector; and a computing device that simultaneously computes the internal quantum efficiency and the external quantum efficiency of the solar cell.

Abstract translation: 使用发射光的同时测量太阳能电池的内部量子效率和外部量子效率; 三光束分离器，其将光分解成太阳能电池光和参考光，其中太阳能电池光照射到太阳能电池; 检测参考光的参考检测器; 反射光检测器，其检测反射光，其中所述反射光包括从太阳能电池反射的太阳能电池光的一部分; 可操作地耦合到太阳能电池的源计量器; 可操作地耦合到太阳能电池，参考检测器和反射检测器的多路复用器; 以及同时计算太阳能电池的内部量子效率和外部量子效率的计算装置。

公开(公告)号：US20140065788A1

公开(公告)日：2014-03-06

申请号：US14075649

申请日：2013-11-08

Applicant: Intermolecular, Inc.

Inventor： Albert Lee ,  Tony P. Chiang ,  Jason Wright

IPC: H01L21/285 ,  H01L45/00 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L21/28562 ,  C23C16/04 ,  C23C16/45525 ,  H01L21/28158 ,  H01L21/68771 ,  H01L28/40 ,  H01L28/60 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616

Abstract: In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.

Abstract translation: 在本发明的一些实施例中，描述了使用一个或多个小型喷头装置以局部隔离，组合方式在小斑点上使用CVD，PECVD，ALD或PEALD沉积材料的方法。 小型喷头可配置在更大的组合喷淋头内，以允许以组合方式沉积多层胶片堆叠。

公开(公告)号：US20140001431A1

公开(公告)日：2014-01-02

申请号：US14018719

申请日：2013-09-05

Applicant: Intermolecular Inc.

Inventor： Pragati KUMAR ,  Tony P. Chiang ,  Prashant B. Phatak ,  Yun Wang

IPC: H01L45/00

CPC classification number: H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

Abstract translation: 本公开提供了一种非易失性存储器件及相关的制造和操作方法。 该装置可以包括一个或多个电阻随机存取存储器（ReRAM）方法来为存储器装置提供更可预测的操作。 特别地，可以通过使用阻挡层，反极性形成电压脉冲，从下功函电极注入电子的形成电压脉冲或还原环境中的退火来降低特定设计所需的形成电压 。 可以根据期望的应用和结果应用这些技术中的一种或多种。

公开(公告)号：US08599603B2

公开(公告)日：2013-12-03

申请号：US13829378

申请日：2013-03-14

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G Malhotra

IPC: G11C11/00

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。