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171.发明申请公开(公告)号：US20190027205A1
公开(公告)日：2019-01-24
申请号：US15783688
申请日：2017-10-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis , Dragos Dimitriu
IPC: G11C11/4074
Abstract: Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver section, a second driver section, and a third driver section. The first driver section is configured to drive an output terminal toward a first selected one of a first voltage and a second voltage. The second driver section configured to drive the output terminal toward a second selected one of the first voltage and the second voltage. The third driver section configured to drive the output terminal toward the first voltage when each of the first selected one and the second selected one is the first voltage. The third driver circuit is further configured to be in a high impedance state when the first selected one and the second selected one are different from each other.
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公开(公告)号：US10043557B1
公开(公告)日：2018-08-07
申请号：US15729393
申请日：2017-10-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis
Abstract: Apparatuses and methods for a multi-level communication architectures are disclosed herein. An example apparatus may include an input/output (I/O) circuit comprising a driver circuit configured to convert a first bitstream directed to a first memory device and a second bitstream directed to a second memory device into a single multilevel signal. The driver circuit is further configured to drive the multilevel signal onto a signal line coupled to the first memory device and to the second memory device using a driver configured to drive more than two voltages.
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公开(公告)号：US09946612B2
公开(公告)日：2018-04-17
申请号：US14804027
申请日：2015-07-20
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
CPC classification number: G06F11/2005 , G06F11/1008 , G06F11/221 , G06F11/3027 , G06F11/3041 , G06F13/28 , G06F13/4022 , G06F13/4027
Abstract: Implementations of encoding techniques are disclosed. In one embodiment, an encoding system includes a codec device, a switching network, a rerouting circuit, a logic integrated circuit, and memory devices. The codec device includes a plurality of input and output (I/O) ports to transport data signals. The switching network is coupled both to the plurality of I/O ports and to a plurality of channels external to the device. The plurality of I/O ports includes at least one spare channel. The rerouting circuitry is coupled to and configured to control the switching network and the logic integrated circuit has logic circuity including command and decode queueing circuitry, redundancy circuits, and error correction circuitry. The memory devices do include any circuitry included in the logic circuitry. Other systems and apparatuses are also described.
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公开(公告)号：US20170337951A1
公开(公告)日：2017-11-23
申请号：US15159728
申请日：2016-05-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis , Huy T. Vo , Dirgha Khatri
CPC classification number: G11C7/10 , G11C5/04 , G11C7/1006 , G11C7/22
Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.
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公开(公告)号：US09691444B2
公开(公告)日：2017-06-27
申请号：US14076985
申请日：2013-11-11
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
CPC classification number: G11C7/10 , G11C5/02 , G11C7/1003
Abstract: Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack.
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Patent Agency Ranking
公开(公告)号：US09571602B2
公开(公告)日：2017-02-14
申请号：US14635618
申请日：2015-03-02
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
CPC classification number: G06F5/06 , G06F13/38 , G06F13/385 , G06F13/4273 , H04L12/4013 , H04L25/0272 , H04L67/288 , H04Q2213/13036 , H04Q2213/13305
Abstract: Methods and apparatus apparatuses to transfer data between a first device and a second device are disclosed. In various embodiments, an apparatus includes a first device and a second device. The first device includes at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device includes at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel. Other methods and apparatuses are disclosed.
Abstract translation: 公开了在第一设备和第二设备之间传送数据的方法和设备设备。 在各种实施例中，一种装置包括第一装置和第二装置。 第一设备包括耦合到第一信道的至少一个第一非差分发射机，耦合到第二信道的至少一个第二非差分发射机和至少一个差分接收机，用于在第一信道上接收数据比特及其补码， 第二通道并行。 第二设备包括耦合到第一信道的至少一个第一非差分接收器，耦合到第二信道的至少一个第二非差分接收器和至少一个差分发射机，用于在第一信道上发送数据比特及其补码， 第二通道并行。 公开了其他方法和装置。
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公开(公告)号：US20160043885A1
公开(公告)日：2016-02-11
申请号：US14918346
申请日：2015-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis
IPC: H04L25/49
CPC classification number: H04L25/4917 , H03K19/0002 , H04L25/4923 , H04L25/4927
Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.
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公开(公告)号：US09203662B2
公开(公告)日：2015-12-01
申请号：US13865006
申请日：2013-04-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis
CPC classification number: H04L25/4917 , H03K19/0002 , H04L25/4923 , H04L25/4927
Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.
Abstract translation: 公开了诸如涉及发射机电路的装置，其被配置为基于多个数字数字产生多电平信号。 一个这样的发射机电路包括信号输出和被配置为至少部分地基于多个数字数字提供控制信号的编码器。 发射机电路还包括被配置为接收一个或多个控制信号的第一组开关，并且选择性地对信号输出进行第一或第二电压基准。 发射机电路还包括分别提供第三和第四电压参考的第一和第二电压降电路。 第三和第四参考电压具有在第一和第二参考电压之间的电压电平。 发射机电路还包括被配置为接收一个或多个控制信号的第二组开关，并且选择性地将第三或第四电压基准传送到信号输出端。
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公开(公告)号：US09048856B2
公开(公告)日：2015-06-02
申请号：US14320127
申请日：2014-06-30
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
CPC classification number: H03M5/00 , G06F13/4234 , G11C7/02 , G11C7/1006 , Y02D10/14 , Y02D10/151
Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US09047425B2
公开(公告)日：2015-06-02
申请号：US14083062
申请日：2013-11-18
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.
Abstract translation: 本文公开的方法和装置操作以接收由一组时域方面表征的多个周期，以修改多个周期中的至少一些周期的时域方面中的至少一个以产生多个修改周期， 以处理至少一些经修改的周期以产生时域周期，并且至少部分地基于连接时域周期来创建时域信号。
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