公开(公告)号：US20180358073A1

公开(公告)日：2018-12-13

申请号：US15619158

申请日：2017-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US10153021B1

公开(公告)日：2018-12-11

申请号：US15619158

申请日：2017-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

Abstract: Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. The duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US20180102157A1

公开(公告)日：2018-04-12

申请号：US15291711

申请日：2016-10-12

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

公开(公告)号：US09934837B2

公开(公告)日：2018-04-03

申请号：US15057914

申请日：2016-03-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US20180061470A1

公开(公告)日：2018-03-01

申请号：US15246249

申请日：2016-08-24

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2275

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US09281061B2

公开(公告)日：2016-03-08

申请号：US13800622

申请日：2013-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Di Vincenzo ,  Simone Lombardo

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C2211/5645 ,  G11C2213/72

Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.

Abstract translation: 装置和方法利用复制电路来产生用于对诸如相变存储器（PCM）的存储单元的存储器单元进行编程的电压。 通过包括要编程的存储器单元的电路的电流以缩放或非缩放的方式被镜像，并被提供给复制电路的输入。 复制电路表示编程存储单元时应该遇到的电压降。 还向复制电路提供输入电压，其影响复制电路内表示电池电压降的电压降。 然后可以将复制电路上的电压降镜像并提供给偏置包括存储器单元的电路。

公开(公告)号：US08773900B2

公开(公告)日：2014-07-08

申请号：US13974731

申请日：2013-08-23

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Carlo Lisi

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/009

Abstract: Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.

Abstract translation: 本文公开的主题涉及存储器件，更具体地，涉及对存储器单元的编程。

公开(公告)号：US20140078822A1

公开(公告)日：2014-03-20

申请号：US13800622

申请日：2013-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Di Vincenzo ,  Simone Lombardo

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C2211/5645 ,  G11C2213/72

Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.

Abstract translation: 装置和方法利用复制电路来产生用于对诸如相变存储器（PCM）的存储单元的存储器单元进行编程的电压。 通过包括要编程的存储器单元的电路的电流以缩放或非缩放的方式被镜像，并被提供给复制电路的输入。 复制电路表示编程存储单元时应该遇到的电压降。 还向复制电路提供输入电压，其影响复制电路内表示电池电压降的电压降。 然后可以将复制电路上的电压降镜像并提供给偏置包括存储器单元的电路。