公开(公告)号：US20150162433A1

公开(公告)日：2015-06-11

申请号：US14097565

申请日：2013-12-05

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract translation: 第一半导体材料的细长散热片与下层基底层（SOI或本体型）绝缘和形成。 然后形成第二半导体材料的细长的栅极，以在沟道区域上跨过细长的翅片，并且栅极侧壁被侧壁间隔物覆盖。 提供保护材料以覆盖下面的基底层并且在细长门之间限定细长翅片的侧壁上的侧壁间隔物。 位于保护材料侧壁间隔件（但不在细长门下）的细长翅片的第一半导体材料和绝缘材料被去除以形成与沟道区域对准的沟槽。 然后在细长门之间的每个沟槽内外延生长另外的半导体材料，以形成邻近由位于细长栅极下方的第一半导体材料的细长鳍片形成的沟道区域的源极 - 漏极区域。

公开(公告)号：US20150162248A1

公开(公告)日：2015-06-11

申请号：US14097556

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/76205 ,  H01L21/76283 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

Abstract: On a substrate formed of a first semiconductor material, a first overlying layer formed of a second semiconductor material is deposited. A second overlying layer formed of a third semiconductor material is deposited over the first overlying layer. The first and second overlying layers are patterned to define fins, wherein each fin includes a first region formed of the third material over a second region formed of the second material. An oxide material fills the space between the fins. A thermal oxidation is then performed to convert the second region to a material insulating the first region formed of the third material from the substrate. As an optional step, the second region formed of the second material is horizontally thinned before the oxide material is deposited and the thermal oxidation is performed. Once the fins are formed and insulated from the substrate, conventional FinFET fabrication is performed.

Abstract translation: 在由第一半导体材料形成的衬底上沉积由第二半导体材料形成的第一覆盖层。 由第三半导体材料形成的第二覆盖层沉积在第一覆盖层上。 图案化第一和第二覆盖层以限定翅片，其中每个翅片包括在由第二材料形成的第二区域上由第三材料形成的第一区域。 氧化物填充翅片之间的空间。 然后进行热氧化以将第二区域转换为将由第三材料形成的第一区域与衬底绝缘的材料。 作为可选步骤，在沉积氧化物材料并进行热氧化之前，由第二材料形成的第二区域被水平地薄化。 一旦翅片形成并与衬底绝缘，就进行常规的FinFET制造。

公开(公告)号：US20150099334A1

公开(公告)日：2015-04-09

申请号：US14048263

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： QING LIU ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract translation: 一种用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括提供包括具有第一和第二横向相邻应力半导体部分的应力半导体层的受应力的绝缘体上硅（sSOI）晶片。 第一应力半导体部分限定第一有源区。 第二应力半导体部分被未受应力的半导体部分代替。 未受应力的半导体部分包括第一半导体材料。 该方法还包括将第二半导体材料驱动到限定第二有源区的无应力半导体部分的第一半导体材料中。

公开(公告)号：US08956942B2

公开(公告)日：2015-02-17

申请号：US13725528

申请日：2012-12-21

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate during fabrication of the device. Similarly, source/drain-to-substrate leakage in a FinFET device is prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. Forming such an insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. In an array of semiconducting fins made up of a multi-layer stack, the bottom material is removed, thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material is then filled with oxide to better support the fins and to isolate the array of fins from the substrate.

Abstract translation: 通过在器件的制造期间在半导体沟道（鳍）和衬底之间插入绝缘层来防止FinFET器件中的沟道到衬底泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层来隔离源极/漏极区域来防止FinFET器件中的源极/漏极到衬底泄漏。 形成这样的绝缘层将物理和电气上的导电路径与衬底隔离，从而防止电流泄漏。 在由多层堆叠构成的半导体鳍阵列中，去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后在剩余的顶部翅片材料下面形成的间隙填充氧化物以更好地支撑翅片并且将翅片阵列与基底隔离开。

公开(公告)号：US20150011060A1

公开(公告)日：2015-01-08

申请号：US14327343

申请日：2014-07-09

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L21/266

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/161 ,  H01L29/6656

Abstract: Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.

Abstract translation: 在集成电路中，在n型和p型区域上形成邻近栅电极的硅锗区。 通过光刻图案化的硬掩模即使在栅电极上的侧壁间隔物上的硬掩模的残留物上，也可以在p型区域上保护结构，同时从n型区域上选择性地去除硅锗。 锗栅极外延生长硅代替去除的硅锗，并且在去除p型区域结构之前的剩余硬掩模之前进行源极/漏极延伸植入。

公开(公告)号：US20140357060A1

公开(公告)日：2014-12-04

申请号：US13903630

申请日：2013-05-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 制造硅 - 锗半导体材料的外延生长以覆盖底部。 然后将锗从外延生长的硅 - 锗材料驱动到底部，以将底部部​​分转化为硅 - 锗。 执行进一步的硅 - 锗生长以在与第一区域中的硅区域相邻的第二区域中限定硅 - 锗区域。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20140357039A1

公开(公告)日：2014-12-04

申请号：US13907237

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Nicolas Loubet ,  Bruce Doris

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L29/0649

Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.

Abstract translation: 在由第一半导体层，绝缘层和第二半导体层形成的衬底上，沉积氧化硅衬垫层和氮化硅衬垫层以形成掩模。 掩模用于打开通过第一半导体层和绝缘层并进入第二半导体层的沟槽。 二氧化硅和氮化硅的双衬垫共形沉积在沟槽内。 沟槽填充有二氧化硅。 氢氟酸蚀刻将氮化硅衬垫层与一部分共形氮化硅衬垫一起去除。 热磷酸蚀刻去除氧化硅衬垫层，填充沟槽的氧化硅的一部分和保形氮化硅衬垫的一部分。 双衬垫在第一和第二半导体层之间的沟槽的边缘处防止衬底蚀刻。

公开(公告)号：US20140353717A1

公开(公告)日：2014-12-04

申请号：US13907411

申请日：2013-05-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

IPC: H01L29/786 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.

Abstract translation: 一种具有沟道外延硅的改进晶体管。 在一个方面，一种制造方法包括：在设置在衬底上的外延硅区域上形成栅极叠层结构，外延硅区域的宽度尺寸接近栅叠层结构的宽度尺寸; 以及从衬底生长升高的外延源和漏极，所述升高的外延源极和漏极与外延硅区域和栅极堆叠结构接触。 对于SRAM器件，进一步：去除与硅衬底和升高的源极和漏极接触的外延层，并且外延硅区域耦合到外延层，留下硅衬底上方的空间，并且在升高的外延源极和漏极之下; 并用绝缘层填充该空间，并将该凸起的外延源极和漏极以及晶体管的沟道与硅衬底隔离。

公开(公告)号：US20140353714A1

公开(公告)日：2014-12-04

申请号：US13905534

申请日：2013-05-30

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Douglas LaTulipe ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。

公开(公告)号：US20140291749A1

公开(公告)日：2014-10-02

申请号：US13852645

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prasanna KHARE ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。